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SP6132HCU Datasheet(PDF) 10 Page - Sipex Corporation |
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SP6132HCU Datasheet(HTML) 10 Page - Sipex Corporation |
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10 / 10 page  10 Date:2/14/06 SP6132H High Voltage, Synchronous PWM Controller © Copyright 2006 Sipex Corporation thermal improvement can be achieved in the maxi- mum power dissipation through the proper design of copper mounting pads on the circuit board. For example, in an SO-8 package, placing two 0.04 square inches of copper pad directly under the package,withoutoccupyingadditionalboardspace, can increase the maximum power from approxi- mately 1 to 1.2W. For DPAK package, enlarging the tap mounting pad to 1 square inch reduces the RΘJA from 96°C/W to 40°C/W. APPLICATIONS INFORMATION: Continued Schottky Diode Selection When paralleled with the bottom MOSFET, an optional Schottky diode can improve efficiency and reduce noise. Without this Schottky diode, the body diode of the bottom MOSFET con- ducts the current during the non-overlap time when both MOSFETs are turned off. Unfortu- nately, the body diode has high forward voltage and reverse recovery problems. The reverse recovery of the body diode causes additional switching noises when the diode turns off. The Schottky diode alleviates these noise sources and additionally improves efficiency thanks to its low forward voltage. The reverse voltage across the diode is equal to input voltage, and the diode must be able to handle the peak current equal to the maximum load current. The power dissipation of the Schottky diode is determined by: PDIODE = 2VFIOUTTNOLFS where TNOL = non-overlap time between GH and GL. VF = forward voltage of the Schottky diode. Loop Compensation Design The open loop gain of the whole system can be divided into the gain of the error amplifier, PWM modulator, buck converter output stage, and feedback resistor divider. In order to cross over at the selected frequency FCO, the gain of the error amplifier must compensate for the attenuation caused by the rest of the loop at this frequency. (SRz2Cz2+1)(SR1Cz3+1) (SRESRCOUT+ 1) [S^2LC OUT+S(RESR+RDC) COUT+1] VIN SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1) VRAMP_PP VOUT (Volts) + _ VREF (Volts) Notes: R ESR = Output Capacitor Equivalent Series Resistance. R DC = Output Inductor DC Resistance. V RAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 Output Load Resistance >> R ESR & RDC R2 VREF (R1 + R2) or VOUT VFBK (Volts) Type III Voltage Loop Compensation G AMP (s) Gain Block PWM Stage G PWM Gain Block Output Stage G OUT (s) Gain Block Voltage Feedback G FBK Gain Block SP6132H Voltage Mode Control Loop with Loop Dynamic |
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