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EPF10K50S Datasheet(PDF) 9 Page - Altera Corporation |
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EPF10K50S Datasheet(HTML) 9 Page - Altera Corporation |
9 / 100 page Altera Corporation 9 FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 1 shows a block diagram of the FLEX 10KE architecture. Each group of LEs is combined into an LAB; groups of LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect routing structure. IOEs are located at the end of each row and column of the FastTrack Interconnect routing structure. Figure 1. FLEX 10KE Device Block Diagram FLEX 10KE devices provide six dedicated inputs that drive the flipflops’ control inputs and ensure the efficient distribution of high-speed, low- skew (less than 1.5 ns) control signals. These signals use dedicated routing channels that provide shorter delays and lower skews than the FastTrack Interconnect routing structure. Four of the dedicated inputs drive four global signals. These four global signals can also be driven by internal logic, providing an ideal solution for a clock divider or an internally generated asynchronous clear signal that clears many registers in the device. I/O Element (IOE) Logic Array Block (LAB) Row Interconnect IOE IOE IOE IOE IOE IOE IOE Local Interconnect IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE Logic Element (LE) Column Interconnect IOE EAB EAB Logic Array IOE IOE IOE IOE IOE IOE Embedded Array Block (EAB) Embedded Array IOE IOE Logic Array IOE IOE |
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