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EPF10K50EFC484-1 Datasheet(PDF) 58 Page - Altera Corporation |
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EPF10K50EFC484-1 Datasheet(HTML) 58 Page - Altera Corporation |
58 / 100 page 58 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Table 26. EAB Timing Microparameters Note (1) Symbol Parameter Conditions tEABDATA1 Data or address delay to EAB for combinatorial input tEABDATA2 Data or address delay to EAB for registered input tEABWE1 Write enable delay to EAB for combinatorial input tEABWE2 Write enable delay to EAB for registered input tEABRE1 Read enable delay to EAB for combinatorial input tEABRE2 Read enable delay to EAB for registered input tEABCLK EAB register clock delay tEABCO EAB register clock-to-output delay tEABBYPASS Bypass register delay tEABSU EAB register setup time before clock tEABH EAB register hold time after clock tEABCLR EAB register asynchronous clear time to output delay tAA Address access delay (including the read enable to output delay) tWP Write pulse width tRP Read pulse width tWDSU Data setup time before falling edge of write pulse (5) tWDH Data hold time after falling edge of write pulse (5) tWASU Address setup time before rising edge of write pulse (5) tWAH Address hold time after falling edge of write pulse (5) tRASU Address setup time with respect to the falling edge of the read enable tRAH Address hold time with respect to the falling edge of the read enable tWO Write enable to data output valid delay tDD Data-in to data-out valid delay tEABOUT Data-out delay tEABCH Clock high time tEABCL Clock low time |
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