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APW8822AQBI-TRL Datasheet(PDF) 11 Page - Anpec Electronics Coropration |
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APW8822AQBI-TRL Datasheet(HTML) 11 Page - Anpec Electronics Coropration |
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11 / 27 page  Copyright © ANPEC Electronics Corp. Rev. A.2 - Nov., 2012 APW8822/A/B/C www.anpec.com.tw 11 Pin Description (Cont.) PIN NO. APW8822/B/C APW8822A NAME FUNCTION 11 11 LGATE2 Output of The Low-Side MOSFET Driver for PWM2. Connect this pin to Gate of the low-side MOSFET. Swings from PGND to LDO5. 12 12 VIN Battery voltage input pin. VIN powers linear regulators and is also used for the constant on-time PWM on-time one-shot circuits. Connect VIN to the battery input and bypass with a 1 µF capacitor for noise interference. 13 13 LDO5 5V Linear Regulator Output. LDO5 can provide a total of 100mA, 5V external loads. When LDO5 is at 5V and PWM1 output voltage is over 4.7V bypass threshold, the internal LDO will shut down, and LDO5 output pin connects to VOUT1 through a 1.5 Ω switch. Bypass to GND with a minimum of 1.0uF ceramic capacitor for stability. 14 14 BYP BYP is the input pin of switchover voltage for the LDO5. This pin makes a direct measurement of the PWM1 output voltage. 15 15 LGATE1 Output of The Low-Side MOSFET Driver for PWM1. Connect this pin to Gate of the low-side MOSFET. Swings from PGND to LDO5. 16 16 UGATE1 Output of The High-Side MOSFET Driver for PWM1. Connect this pin to Gate of the high-side MOSFET. 17 17 BOOT1 Supply Input for The UGATE1 Gate Driver and an internal level-shift circuit. Connect to an external capacitor to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. 18 18 PHASE1 Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain for PWM1. Connect this pin to the Source of the high-side MOSFET. PHASE1 serves as the lower supply rail for the UGATE1 high-side gate driver. PHASE1 is the current-sense input for the PWM1. 19 19 VCLK 250kHz Clock Output for 15V Charge Pump. 20 - EN1 PWM1 Enable. PWM1 is enabled when EN1=1. When EN1=0, PWM1 is in shutdown. - 20 ENLDO Master Enable Input. The LDOx is enabled when ENLDO=1. When ENLDO=0, the LDOx is shutdown. See the table2 “ Power-Up Control Logics”. Thermal Pad Thermal Pad GND Signal Ground for The IC. |
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