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APW8813AQBI-TRG Datasheet(PDF) 8 Page - Anpec Electronics Coropration |
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APW8813AQBI-TRG Datasheet(HTML) 8 Page - Anpec Electronics Coropration |
8 / 31 page Copyright © ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 APW8813/A www.anpec.com.tw 8 Pin Description PIN APW8813 APW8813A NAME FUNCTION 1 1 VTTGND Power ground output for the VTT LDO. 2 2 VTTSNS Voltage sense input for the V TT LDO. Connect to plus terminal of the VTT LDO output capacitor. 3 3 GND Signal ground for the PWM control ler and VTT LDO. Connect to minus terminal of the VTT LDO output capacitor. 4 - MODE Discharge mode setting pin. When this pin connects to VCC, it is no discharge state. When this pin connects to VDDQ, it is tracking discharge state. When this pin connects to GND, it is non-tracking discharge state. 5 4 VTTREF VTTREF buffered reference ou tput. 6 - FCCM Selection pin for PWM controller to operate in either forced PWM or automatic PWM/PFM mode. Force PWM mode is enabl e when FCCM pin is pulled below the falling threshold voltage VFCCMTHF, and force PWM is disabled when the FCCM pin is pulled above the rising threshold voltage VFCCMTHR. 7 - NC No Connection. 8 5 V DDQSNS VDDQ reference input for VTT and VTTREF. Power supply fo r the VTTREF. Discharge current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to VCC or GND. 9 6 VDDQSET VDDQ output voltage setting pin. 10 7 S3 S3 signal input. 11 8 S5 S5 signal input. 12 9 TON This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor RTON from TON pin to PHASE VIN terminal. 13 10 PGOOD Power-good output pin. PGOOD i s an open drain output used to Indicate the status of the output voltage. When VDDQ output voltage is within the ta rget range, it is in high state. 14 11 VCC Filtered 5V power supply input for internal control circuitry. Connect R-C network from PVCC to VCC. 15 12 PVCC 5V power supply voltage input pin for low-side MOSFET gate driver on TQFN-24 package. 16 13 CS Over-current trip voltage setting input for RDS(ON) current sense scheme if connected to VCC through the voltage setting resistor. 17 - CS_GND Current sense comparator posi tive input terminal and the ground for power good circuit. 18 14 PGND Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the low-side MOS FET. Also i t is current sense comparator positive input terminal and the ground of power good circuit on SSOP-20 package. 19 15 LGATE Output of the low-side MOSFET driver for PWM. C onnect this pin to Gate of the low-side MOSFET. Swings from PGND to VCC. 20 16 P HASE Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UGATE high-side gate driver. 21 17 UGATE Output of the high-side MOSFE T driver for PWM. Connect this pin to Gate of the high-side MOSFET. 22 18 BOOT Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an external capacitor and diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. 23 19 LDOIN Supply voltage input for the VTT LDO. 24 20 VTT Power output for the VTT LDO. |
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