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APW7098 Datasheet(PDF) 25 Page - Anpec Electronics Coropration

Part No. APW7098
Description  Two- Phase Buck PWM Controller with Integrated MOSFET Drivers
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Maker  ANPEC [Anpec Electronics Coropration]
Homepage  http://www.anpec.com.tw
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APW7098 Datasheet(HTML) 25 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.7 - Oct., 2011
APW7098
www.anpec.com.tw
25
Application Information (Cont.)
Layout Consideration (Cont.)
The signals going through theses traces have both
high dv/dt and high di/dt with high peak charging and
discharging current. The traces from the gate drivers
to the MOSFETs (UGATEx and LGATEx) should be short
and wide.
Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane be-
tween the two pads reduces the voltage bounce of
the node. In addition, the large layout plane between
the drain of the MOSFETs (V
IN and PHASEx nodes)
can get better heat sinking.
For experiment result of accurate current sensing, the
current sensing components are suggested to place
close to the inductor part. To avoid the noise
interference, the current sensing trace should be away
from the noisy switching nodes.
Decoupling capacitors, the resistor-divider, and boot
capacitor should be close to their pins. (For example,
place the decoupling ceramic capacitor close to the
drain of the high-side MOSFET as close as possible).
The input bulk capacitors should be close to the drain
of the high-side MOSFET, and the output bulk capaci-
tors should be close to the loads. The input capaci-
tor’s ground should be close to the grounds of the
output capacitors and low-side MOSFET.
Locate the resistor-divider close to the FB pin to mini-
mize the high impedance trace. In addition, FB pin
traces can’t be close to the switching signal traces
(UGATEx, LGATEx, BOOTx, and PHASEx).
Keep the switching nodes (UGATEx, LGATEx, BOOTx,
and PHASEx) away from sensitive small signal nodes
since these nodes are fast moving signals. Therefore,
keep traces to these nodes as short as possible and
there should be no other weak signal traces in paral-
lel with theses traces on any layer.
Figure 10. Layout Guidelines
BOOT1
PHASE1
UGATE1
LGATE1
V
IN1=V IN
APW7098
V
IN2 =V IN
BOOT2
PHASE2
UGATE2
LGATE2
V
OUT
L
O
A
D
C
S1
CSP1
CSN1
R
S1
CSP2
CSN2
R
S2
L1
L2
C
S2


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