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APW7098 Datasheet(PDF) 22 Page - Anpec Electronics Coropration

Part No. APW7098
Description  Two- Phase Buck PWM Controller with Integrated MOSFET Drivers
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Maker  ANPEC [Anpec Electronics Coropration]
Homepage  http://www.anpec.com.tw
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APW7098 Datasheet(HTML) 22 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.7 - Oct., 2011
APW7098
www.anpec.com.tw
22
Application Information (Cont.)
PWM Compensation (Cont.)
The pole and zero frequencies of the transfer function
are:
Figure 8. Compensation Network
C2
R2
2
1
F
Z1
×
×
π
×
=
(
) C3
R3
R1
2
1
F
Z2
×
+
×
π
×
=
+
×
×
×
π
×
=
C2
C1
C2
C1
R2
2
1
F
P1
C3
R3
2
1
F
P2
×
×
π
×
=
The closed loop gain of the converter can be written as:
GAIN
LC X GAINPWM X GAINAMP
Figure 9. shows the asymptotic plot of the closed loop
converter gain, and the following guidelines will help to
design the compensation network. Using the below
guidelines should give a compensation similar to the
curve plotted. A stable closed loop has a -20dB/ decade
slope and a phase margin greater than 45 degree.
1. Choose a value for R1, usually between 1K and 5K.
2. Select the desired zero crossover frequency
F
O= (1/5 ~ 1/10) X FSW
Use the following equation to calculate R2:
3. Place the first zero F
Z1 before the output LC filter double
pole frequency F
LC.
F
Z1 = 0.75 X FLC
Calculate the C2 by the equation:
R1
F
F
V
V
R2
LC
O
IN
OSC
×
×
=
4. Set the pole at the ESR zero frequency F
ESR:
F
P1 = FESR
Calculate the C1 by the following equation:
0.75
F
R2
2
1
C2
LC ×
×
×
π
×
=
1
F
C2
R2
2
C2
C1
ESR
×
×
×
π
×
=
5. Set the second pole F
P2 at the half of the switching
frequency and also set the second zero F
Z2 at the output LC
filter double pole F
LC. The compensation gain should not
exceed the error amplifier open loop gain, check the
compensation gain at F
P2 with the capabilities of the
error amplifier.
F
P2 = 0.5 X FSW
F
Z2 = FLC
Combine the two equations will get the following
component calculations:
F
LC
Frequency(Hz)
20log
(R2/R1)
20log
(V
IN/ΔVOSC)
F
Z1
F
Z2
F
P1
F
P2
F
ESR
PWM & Filter Gain
Converter Gain
Compensation Gain
V
REF
V
OUT
V
COMP
R1
R3
C3
R2
C2
C1
FB
1
F
2
F
R1
R3
LC
SW
×
=
SW
F
R3
1
C3
×
×
π
=
Figure 9. Converter Gain and Frequency
Output Inductor Selection
The duty cycle (D) of a buck converter is the function of
the input voltage and output voltage. Once an output volt-
age is fixed, it can be written as:


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