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AS6C4008-55TIN Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation

Part No. AS6C4008-55TIN
Description  512K X 8 BIT LOW POWER 512K X 8 BIT LOW POWER CMOS SRAM
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Maker  ALSC [Alliance Semiconductor Corporation]
Homepage  http://www.alsc.com
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AS6C4008-55TIN Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation

 
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WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Dout
Din
Data Valid
tDW
tDH
(4)
High-Z
tWHZ
WE#
tWP
tCW
CE#
tWR
tAS
tAW
Address
tWC
(4)
TOW
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
Dout
Din
Data Valid
tDW
tDH
(4)
High-Z
tWHZ
WE#
tWP
tCW
CE#
tWR
tAS
tAW
Address
tWC
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
®
512K X 8 BIT LOW POWER CMOS SRAM
OCTOBER 2007
AS6C4008
10/OCTOBER/07, V.1.1
Alliance Memory Inc.
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