LPC11U35FET48 datasheet(30/76 Pages) NXP

Part #	LPC11U35FET48

Description	32-bit ARM Cortex-M0 microcontroller up to 128 kB flash up to 12 kB SRAM and 4 kB EEPROM USB device USART

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Manufacturer	NXP [NXP Semiconductors]

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LPC11U3X

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Product data sheet

Rev. 2 — 25 November 2013

30 of 76

NXP Semiconductors

LPC11U3x

32-bit ARM Cortex-M0 microcontroller

7.19 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are

supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is

configured to support up to four breakpoints and two watch points.

The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM

SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the

LPC11U3x is in reset.

To perform boundary scan testing, follow these steps:

1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.

3. Wait for at least 250

s.

4. Pull the RESET pin LOW externally.

5. Perform boundary scan operations.

6. Once the boundary scan operations are completed, assert the TRST pin to enable the

SWD debug mode, and release the RESET pin (pull HIGH).

Remark: The JTAG interface cannot be used for debug purposes.

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