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FXLC95000CL Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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FXLC95000CL Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 38 page  External clock domain Internal clock domain Analog Front End SDA1,SCL1 8 BKGD/MS Temperature sensor Drive circuit C2V ADC Peripheral bus interface Trim 3-axis accelerometer transducer System Integration Module Interrupt controller 16 KB RAM ColdFire V1 16 KB ROM 128 KB Flash memory RGPIO[15:0] Flash controller I2C master SPI master 2 x 8 Port control 16-bit modulo timer Programmable Delay Block Two-channel TPM Clock module (16 MHz) Control and mailbox register set SPI slave I2C slave 16 16 8 16 8 8 16 8 8 16 8 / / / SCLK2. SSB2 MOSI, MISO, SP_SCR[PS] SSB SCLK MISO MOSI SDA0 SCL0 RESETB INT_I CPU / / PDB_A, PDB_B TPMCH0, TPMCH1 RGPIO0, ... , RGPIO15 Figure 1. Block diagram of the FXLC95000CL A block level view of the FXLC95000CL platform is shown in Figure 1 and can be summarized at a high level as an analog/mixed mode subsystem associated with a digital engine. The analog sub-system is composed of: • A 3-axis MEMS transducer • An Analog Front End (AFE) with: • A capacitance-to-voltage converter • An analog-to-digital converter • A temperature sensor The digital sub-system is composed of: • A 32-bit, ColdFire V1 CPU with Background Debug Module (BDM) • Memory: RAM, ROM, and flash • Rapid General Purpose Input/Output (RGPIO) port control logic • Timer functions: • Modulo Timer Module (MTIM16) • Programmable Delay Timer (PDB) • General-Purpose Timer/Pulse-Width Modulation Module (TPM) General Description 6 Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013. Freescale Semiconductor, Inc. |
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