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AD5122A Datasheet(PDF) 26 Page - Analog Devices

Part No. AD5122A
Description  Quad Channel, 128-/256-Position, I2C Nonvolatile Digital Potentiometer
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD5122A Datasheet(HTML) 26 Page - Analog Devices

 
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AD5123/AD5143
Data Sheet
Rev. A | Page 26 of 28
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous
current of ±6 mA or to the pulse current specified in Table 5.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 38.
W
A
B
VA
VOUT
VB
Figure 38. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
B
AB
AW
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
(7)
where:
RWB(D)
can be obtained from Equation 1 and Equation 2.
RAW(D)
can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE
The AD5123/AD5143 are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
VDD
A
W
B
VSS
Figure 39. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 39), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, digital inputs, and VA, VB,
and VW. The order of powering VA, VB, VW, and digital inputs is
not important as long as they are powered after VSS and VDD.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD is powered, the power-on preset
activates, which restores EEPROM values to the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 40 illustrates the basic supply bypassing configuration
for the AD5123/AD5143.
VSS
VDD
+
VDD
C1
0.1µF
C3
10µF
+
C2
0.1µF
C4
10µF
VSS
AD5123/
AD5143
GND
Figure 40. Power Supply Bypassing


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