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AD5045 Datasheet(PDF) 5 Page - Analog Devices |
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AD5045 Datasheet(HTML) 5 Page - Analog Devices |
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5 / 28 page  Data Sheet AD5024/AD5044/AD5064 Rev. F | Page 5 of 28 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter1 Symbol Min Typ Max Unit SCLK Cycle Time t1 20 ns SCLK High Time t2 10 ns SCLK Low Time t3 10 ns SYNC to SCLK Falling Edge Setup Time t4 17 ns Data Setup Time t5 5 ns Data Hold Time t6 5 ns SCLK Falling Edge to SYNC Rising Edge t7 5 30 ns Minimum SYNC High Time (Single Channel Update) t8 3 µs Minimum SYNC High Time (All Channel Update) t8 8 µs SYNC Rising Edge to SCLK Fall Ignore t9 17 ns LDAC Pulse Width Low t10 20 ns SCLK Falling Edge to LDAC Rising Edge t11 20 ns CLR Minimum Pulse Width Low t12 10 ns SCLK Falling Edge to LDAC Falling Edge t13 10 ns CLR Pulse Activation Time t14 10.6 µs SCLK Rising Edge to SDO Valid t152, 3 22 ns SCLK Falling Edge to SYNC Rising Edge t162 5 ns SYNC Rising Edge to SCLK Rising Edge t172 8 ns SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update) t182 2 µs SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update) t182 8 µs Power-up Time4 4.5 µs 1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested. 2 Daisy-chain mode only. 3 Measured with the load circuit of Figure 3. t15 determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only. 4 Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32nd clock edge to 90% of DAC midscale value, with output unloaded. Circuit and Timing Diagrams 2mA IOL 2mA IOH TO OUTPUT PIN CL 50pF 2 VOH (MIN) + VOL (MAX) Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications |
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