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AD2S80ASD Datasheet(PDF) 9 Page - Analog Devices |
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AD2S80ASD Datasheet(HTML) 9 Page - Analog Devices |
9 / 16 page AD2S80A REV. B –9– DATA TRANSFER To transfer data the INHIBIT input should be used. The data will be valid 600 ns after the application of a logic “LO” to the INHIBIT. This is regardless of the time when the INHIBIT is applied and allows time for an active BUSY to clear. By using the ENABLE input the two bytes of data can be transferred after which the INHIBIT should be returned to a logic “HI” state to enable the output latches to be updated. BUSY Output The validity of the output data is indicated by the state of the BUSY output. When the input to the converter is changing, the signal appearing on the BUSY output is a series of pulses at TTL level. A BUSY pulse is initiated each time the input moves by the analog equivalent of one LSB and the internal counter is incremented or decremented. INHIBIT Input The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. Releasing the INHIBIT automatically generates a BUSY pulse to refresh the output data. ENABLE Input The ENABLE input determines the state of the output data. A logic “HI” maintains the output data pins in the high imped- ance condition, and the application of a logic “LO” presents the data in the latches to the output pins. The operation of the ENABLE has no effect on the conversion process. BYTE SELECT Input The BYTE SELECT input selects the byte of the position data to be presented at the data output DB1 to DB8. The least signifi- cant byte will be presented on data output DB9 to DB16 (with the ENABLE input taken to a logic “LO”) regardless of the state of the BYTE SELECT pin. Note that when the AD2S80A is used with a resolution less than 16 bits the unused data lines are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input will present the eight most significant data bits on data output DB1 and DB8. A logic “LO” will present the least significant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will dupli- cate data outputs 9 to 16. The operation of the BYTE SELECT has no effect on the con- version process of the converter. RIPPLE CLOCK As the output of the converter passes through the major carry, i.e., all “1s” to all “0s” or the converse, a positive going edge on the RIPPLE CLOCK (RC) output is initiated indicating that a revolution, or a pitch, of the input has been completed. The minimum pulse width of the ripple clock is 300 ns. RIPPLE CLOCK is normally set high before a BUSY pulse and resets before the next positive going edge of the next consecutive pulse. The only exception to this is when DIR changes while the RIPPLE CLOCK is high. Resetting of the RIPPLE clock will only occur if the DIR remains stable for two consecutive posi- tive BUSY pulse edges. If the AD2S80A is being used in a pitch and revolution count- ing application, the ripple and busy will need to be gated to prevent false decrement or increment (see Figure 2). RIPPLE CLOCK is unaffected by INHIBIT. IN4148 IN4148 RIPPLE CLOCK 5V 5k BUSY 5V 10k 1k 0V TO COUNTER (CLOCK) NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS "LO." 2N3904 Figure 2. Diode Transistor Logic Nand Gate DIRECTION Output The DIRECTION (DIR) logic output indicates the direction of the input rotation. Any change in the state of DIR precedes the corresponding BUSY, DATA and RIPPLE CLOCK updates. DIR can be considered as an asynchronous output and can make multiple changes in state between two consecutive LSB update cycles. This corresponds to a change in input rotation direction but less than 1 LSB. DIGITAL TIMING t4 BUSY RIPPLE CLOCK DATA DIR DATA BYTE SELECT DATA INHIBIT INHIBIT ENABLE VH VL VH VH VL VH VH VL VL VL VH VL VL VZ VH VH VL t13 t12 t10 t7 t6 t2 t1 t3 t5 t9 t11 t8 PARAMETER TMIN TMAX CONDITION t1 200 600 BUSY WIDTH VH–VH t2 10 25 RIPPLE CLOCK VH TO BUSY VH t3 470 580 RIPPLE CLOCK VL TO NEXT BUSY VH t4 16 45 BUSY VH TO DATA VH t5 3 25 BUSY VH TO DATA VL t6 70 140 INHIBIT V H TO BUSY VH t7 485 625 MIN DIR VH TO BUSY VH t8 515 670 MIN DIR VH TO BUSY VH t9 – 600 INHIBIT V L TO DATA STABLE t10 40 110 ENABLE V L TO DATA VH t11 35 110 ENABLE V L TO DATA VL t12 60 140 BYTE SELECT VL TO DATA STABLE t13 60 125 BYTE SELECT VH TO DATA STABLE |
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