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TOP254PN Datasheet(PDF) 10 Page - Power Integrations, Inc.

Part No. TOP254PN
Description  Enhanced EcoSmart®, Integrated Off-Line Switcher with Advanced Feature Set and Extended Power Range
Download  48 Pages
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Maker  POWERINT [Power Integrations, Inc.]
Homepage  http://www.powerint.com
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TOP254PN Datasheet(HTML) 10 Page - Power Integrations, Inc.

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Rev. F 01/09
10
TOP252-262
www.powerint.com
On-Chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET on-state drain
to source voltage V
DS(ON) with a threshold voltage.
High drain
current causes V
DS(ON) to exceed the threshold voltage and turns
the output MOSFET off until the start of the next clock cycle.
The current limit comparator threshold voltage is temperature
compensated to minimize the variation of the current limit due
to temperature related changes in R
DS(ON) of the output MOSFET.
The default current limit of TOPSwitch-HX is preset internally.
However, with a resistor connected between EXTERNAL
CURRENT LIMIT (X) pin (Y, E/L and M packages) or MULTI-
FUNCTION (M) pin (P and G package) and SOURCE pin (for
TOP259-261 Y, the X pin is connected to the SIGNAL GROUND
(G) pin), current limit can be programmed externally to a lower
level between 30% and 100% of the default current limit. By
setting current limit low, a larger TOPSwitch-HX than necessary
for the power required can be used to take advantage of the
lower R
DS(ON) for higher efficiency/smaller heat sinking
requirements. TOPSwitch-HX current limit reduction initial
tolerance through the X pin (or M pin) has been improved
significantly compare with previous TOPSwitch-GX. With a
second resistor connected between the EXTERNAL CURRENT
LIMIT (X) pin (Y, E/L and M packages) or MULTI-FUNCTION (M)
pin (P and G package) and the rectified DC high voltage bus,
the current limit is reduced with increasing line voltage, allowing
a true power limiting operation against line variation to be
implemented. When using an RCD clamp, this power limiting
technique reduces maximum clamp voltage at high line. This
allows for higher reflected voltage designs as well as reducing
clamp dissipation.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by
primary-side capacitances and secondary-side rectifier reverse
recovery time should not cause premature termination of the
switching pulse.
The current limit is lower for a short period after the leading
edge blanking time. This is due to dynamic characteristics of
the MOSFET. During startup and fault conditions the controller
prevents excessive drain currents by reducing the switching
frequency.
Line Undervoltage Detection (UV)
At power up, UV keeps TOPSwitch-HX off until the input line
voltage reaches the undervoltage threshold. At power down,
UV prevents auto-restart attempts after the output goes out of
regulation. This eliminates power down glitches caused by slow
discharge of the large input storage capacitor present in
applications such as standby supplies. A single resistor
connected from the VOLTAGE-MONITOR pin (Y, E/L and M
packages) or MULTI-FUNCTION pin (P and G packages) to the
rectified DC high voltage bus sets UV threshold during power
up. Once the power supply is successfully turned on, the UV
threshold is lowered to 44% of the initial UV threshold to allow
extended input voltage operating range (UV low threshold). If
the UV low threshold is reached during operation without the
power supply losing regulation, the device will turn off and stay
off until UV (high threshold) has been reached again. If the
power supply loses regulation before reaching the UV low
threshold, the device will enter auto-restart. At the end of each
auto-restart cycle (S15), the UV comparator is enabled. If the
UV high threshold is not exceeded, the MOSFET will be
disabled during the next cycle (see Figure 11). The UV feature
can be disabled independent of the OV feature.
PI-4531-121206
S13 S12
S0
S15
S13
S12
S0
S15
S14
S13
S15
S14
S14
5.8 V
4.8 V
S15
0 V
0 V
0 V
V
LINE
V
C
V
DRAIN
V
OUT
Note: S0 through S15 are the output states of the auto-restart counter
2
1
2
3
4
0 V
S0
S15
V
UV
S12
Figure 11. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.


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