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ADSP-BF533SBBC500 Datasheet(PDF) 21 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 21 Page - Analog Devices

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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I
|
Page 21 of 64
|
August 2013
The following three tables describe the voltage/frequency
requirements for the processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock (Table 10 and Table 11) and system clock (Table 13)
specifications. Table 12 describes phase-locked loop operating
conditions.
Table 10. Core Clock (CCLK) Requirements—500 MHz, 533 MHz, and 600 MHz Models
Parameter
Internal Regulator Setting
Max
Unit
fCCLK
CCLK Frequency (VDDINT = 1.3 V Minimum)
1
1.30 V
600
MHz
fCCLK
CCLK Frequency (VDDINT = 1.2 V Minimum)
2
1.25 V
533
MHz
fCCLK
CCLK Frequency (VDDINT = 1.14 V Minimum)
3
1.20 V
500
MHz
fCCLK
CCLK Frequency (VDDINT = 1.045 V Minimum) 1.10 V
444
MHz
fCCLK
CCLK Frequency (VDDINT = 0.95 V Minimum)
1.00 V
400
MHz
fCCLK
CCLK Frequency (VDDINT = 0.85 V Minimum)
0.90 V
333
MHz
fCCLK
CCLK Frequency (VDDINT = 0.8 V Minimum)
0.85 V
250
MHz
1 Applies to 600 MHz models only. See Ordering Guide on Page 63.
2 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 63. 533 MHz models cannot support internal regulator levels above 1.25 V.
3 Applies to 500 MHz, 533 MHz, and 600 MHz models. See Ordering Guide on Page 63. 500 MHz models cannot support internal regulator levels above 1.20 V.
Table 11. Core Clock (CCLK) Requirements—400 MHz Models1
Parameter
TJ = 125°C
All2 Other TJ
Unit
Internal Regulator Setting
Max
Max
fCCLK
CCLK Frequency (VDDINT = 1.14 V Minimum) 1.20 V
400
400
MHz
fCCLK
CCLK Frequency (VDDINT = 1.045 V Minimum) 1.10 V
333
364
MHz
fCCLK
CCLK Frequency (VDDINT = 0.95 V Minimum) 1.00 V
295
333
MHz
fCCLK
CCLK Frequency (VDDINT = 0.85 V Minimum) 0.90 V
280
MHz
fCCLK
CCLK Frequency (VDDINT = 0.8 V Minimum)
0.85 V
250
MHz
1 See Ordering Guide on Page 63.
2 See Operating Conditions on Page 20.
Table 12. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Max fCCLK
MHz
Table 13. System Clock (SCLK) Requirements
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
1
Max
Max
Unit
CSP_BGA/PBGA
fSCLK
CLKOUT/SCLK Frequency (VDDINT  1.14 V)
100
133
MHz
fSCLK
CLKOUT/SCLK Frequency (VDDINT  1.14 V)
100
100
MHz
LQFP
fSCLK
CLKOUT/SCLK Frequency (VDDINT  1.14 V)
100
133
MHz
fSCLK
CLKOUT/SCLK Frequency (VDDINT  1.14 V)
83
83
MHz
1 tSCLK (= 1/fSCLK) must be greater than or equal to tCCLK.


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