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ADSP-BF533SBBC500 Datasheet(PDF) 18 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 18 Page - Analog Devices

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 18 / 64 page
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Rev. I
|
Page 18 of 64
|
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Port F: GPIO/Parallel Peripheral
Interface Port/SPI/Timers
PF0/SPISS
I/O
GPIO/SPI Slave Select Input
C
PF1/SPISEL1/TACLK
I/O
GPIO/SPI Slave Select Enable 1/Timer Alternate Clock Input
C
PF2/SPISEL2
I/O
GPIO/SPI Slave Select Enable 2
C
PF3/SPISEL3/PPI_FS3
I/O
GPIO/SPI Slave Select Enable 3/PPI Frame Sync 3
C
PF4/SPISEL4/PPI15
I/O
GPIO/SPI Slave Select Enable 4/PPI 15
C
PF5/SPISEL5/PPI14
I/O
GPIO/SPI Slave Select Enable 5/PPI 14
C
PF6/SPISEL6/PPI13
I/O
GPIO/SPI Slave Select Enable 6/PPI 13
C
PF7/SPISEL7/PPI12
I/O
GPIO/SPI Slave Select Enable 7/PPI 12
C
PF8/PPI11
I/O
GPIO/PPI 11
C
PF9/PPI10
I/O
GPIO/PPI 10
C
PF10/PPI9
I/O
GPIO/PPI 9
C
PF11/PPI8
I/O
GPIO/PPI 8
C
PF12/PPI7
I/O
GPIO/PPI 7
C
PF13/PPI6
I/O
GPIO/PPI 6
C
PF14/PPI5
I/O
GPIO/PPI 5
C
PF15/PPI4
I/O
GPIO/PPI 4
C
JTAG Port
TCK
I
JTAG Clock
TDO
O
JTAG Serial Data Out
C
TDI
I
JTAG Serial Data In
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This pin should be pulled low if JTAG is not used.)
EMU
O
Emulation Output
C
SPI Port
MOSI
I/O
Master Out Slave In
C
MISO
I/O
Master In Slave Out (This pin should be pulled high through a 4.7 k
 resistor if booting via the
SPI port.)
C
SCK
I/O
SPI Clock
D
Serial Ports
RSCLK0
I/O
SPORT0 Receive Serial Clock
D
RFS0
I/O
SPORT0 Receive Frame Sync
C
DR0PRI
I
SPORT0 Receive Data Primary
DR0SEC
I
SPORT0 Receive Data Secondary
TSCLK0
I/O
SPORT0 Transmit Serial Clock
D
TFS0
I/O
SPORT0 Transmit Frame Sync
C
DT0PRI
O
SPORT0 Transmit Data Primary
C
DT0SEC
O
SPORT0 Transmit Data Secondary
C
RSCLK1
I/O
SPORT1 Receive Serial Clock
D
Table 9. Pin Descriptions (Continued)
Pin Name
Type Function
Driver
Type1


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