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ADSP-BF533SBBC500 Datasheet(PDF) 17 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 17 Page - Analog Devices

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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I
|
Page 17 of 64
|
August 2013
PIN DESCRIPTIONS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors pin
definitions are listed in Table 9.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins. These pins are all
driven high, with the exception of CLKOUT, which toggles at
the system clock rate. During hibernate, all outputs are three-
stated unless otherwise noted in Table 9.
If BR is active (whether or not RESET is asserted), the memory
pins are also three-stated. All unused I/O pins have their input
buffers disabled with the exception of the pins that need pull-
ups or pull-downs as noted in the table.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 9. Pin Descriptions
Pin Name
Type Function
Driver
Type1
Memory Interface
ADDR19–1
O
Address Bus for Async/Sync Access
A
DATA15–0
I/O
Data Bus for Async/Sync Access
A
ABE1–0/SDQM1–0
O
Byte Enables/Data Masks for Async/Sync Access
A
BR
I
Bus Request (This pin should be pulled high if not used.)
BG
OBus Grant
A
BGH
O
Bus Grant Hang
A
Asynchronous Memory Control
AMS3–0
O
Bank Select (Require pull-ups if hibernate is used.)
A
ARDY
I
Hardware Ready Control (This pin should be pulled high if not used.)
AOE
O
Output Enable
A
ARE
ORead Enable
A
AWE
OWrite Enable
A
Synchronous Memory Control
SRAS
O
Row Address Strobe
A
SCAS
O
Column Address Strobe
A
SWE
OWrite Enable
A
SCKE
O
Clock Enable (Requires pull-down if hibernate is used.)
A
CLKOUT
O
Clock Output
B
SA10
O
A10 Pin
A
SMS
O
Bank Select
A
Timers
TMR0
I/O
Timer 0
C
TMR1/PPI_FS1
I/O
Timer 1/PPI Frame Sync1
C
TMR2/PPI_FS2
I/O
Timer 2/PPI Frame Sync2
C
PPI Port
PPI3–0
I/O
PPI3–0
C
PPI_CLK/TMRCLK
I
PPI Clock/External Timer Reference


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