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ADSP-BF533SBBC500 Datasheet(PDF) 1 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 1 Page - Analog Devices

 
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Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Blackfin
Embedded Processor
ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages (see Operating Conditions
on Page 20)
Qualified for Automotive Applications (see Automotive Prod-
ucts on Page 62)
Programmable on-chip voltage regulator
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP
packages
MEMORY
Up to 148K bytes of on-chip memory (see Table 1 on Page 3)
Memory management unit providing memory protection
External memory controller with glueless support for
SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and
external memory
PERIPHERALS
Parallel peripheral interface PPI, supporting
ITU-R 656 video data formats
2 dual-channel, full duplex synchronous serial ports, sup-
porting eight stereo I2S channels
2 memory-to-memory DMAs
8 peripheral DMAs
SPI-compatible port
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA
Event handler
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
Figure 1. Functional Block Diagram
UART
SPORT0
-1
WATCHDOG
TIMER
RTC
SPI
TIMER0
-2
PPI
GPIO
PORT
F
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT ROM
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
DMA
CONTROLLER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
DMA CORE BUS
DMA
EXTERNAL
BUS
EXTERNAL ACCESS BUS
16
INTERRUPT
CONTROLLER
B


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