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ADSP-BF533SBBC500 Datasheet(PDF) 46 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 46 Page - Analog Devices

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Rev. I
|
Page 46 of 64
|
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 47). VLOAD is 0.95 V for VDDEXT
(nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) =
2.5 V/3.3 V. Figure 48 through Figure 59 on Page 48 show how
output rise time varies with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out-
side the ranges shown.
Figure 47. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
T1
ZO = 50
Ω (impedance)
TD = 4.04
± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
Ω
0.5pF
70
Ω
400
Ω
45
Ω
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
Ω
Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 1.75 V
Figure 49. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 2.25 V
Figure 50. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 3.65 V
RISE TIME
FALL TIME
LOAD CAPACITANCE (pF)
0
50
100
150
200
250
16
14
12
10
8
6
4
2
0
LOAD CAPACITANCE (pF)
RISE TIME
14
12
10
8
6
4
2
0
0
50
100
150
200
250
FALL TIME
LOAD CAPACITANCE (pF)
RISE TIME
12
10
8
6
4
2
0
0
50
100
150
200
250
FALL TIME


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