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ADSP-BF533SBBC500 Datasheet(PDF) 42 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 42 Page - Analog Devices

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Rev. I
|
Page 42 of 64
|
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
JTAG Test and Emulation Port Timing
Table 37. JTAG Port Timing
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tTCK
TCK Period
20
20
ns
tSTAP
TDI, TMS Setup Before TCK High
4
4
ns
tHTAP
TDI, TMS Hold After TCK High
4
4
ns
tSSYS
System Inputs Setup Before TCK High
1
1 System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
RESET, NMI, BMODE1–0, BR, PPI3–0.
44
ns
tHSYS
System Inputs Hold After TCK High
1
55
ns
tTRSTW
TRST Pulse Width2 (Measured in TCK Cycles)
2 50 MHz maximum.
44
TCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
10
10
ns
tDSYS
System Outputs Delay After TCK Low
3
3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
0120
12
ns
Figure 32. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
tHSYS
tDSYS


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