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ADSP-BF533SBBC500 Datasheet(PDF) 37 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 37 Page - Analog Devices

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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I
|
Page 37 of 64
|
August 2013
Table 31. External Late Frame Sync
VDDEXT = 1.8 V
LQFP/PBGA Packages
VDDEXT = 1.8 V
CSP_BGA Package
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Switching Characteristics
tDDTLFSE Data Delay from Late External TFSx or External RFSx
in multichannel mode with MCMEN = 01, 2
10.5
10.0
10.0
ns
tDTENLFS Data Enable from Late FS or in multichannel mode
with MCMEN = 01, 2
00
0
ns
1 In multichannel mode, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE.
2 If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
Figure 26. External Late Frame Sync
RSCLKx
RFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
EXTERNAL RFSx IN MULTI-CHANNEL MODE
1ST BIT
tDTENLFSE
tDDTLFSE
TSCLKx
TFSx
DTx
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
LATE EXTERNAL TFSx
1ST BIT
tDDTLFSE


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