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ADSP-BF533SBBC500 Datasheet(PDF) 34 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 34 Page - Analog Devices

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Rev. I
|
Page 34 of 64
|
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Port Timing
Table 28 through Table 31 on Page 37 and Figure 23 on Page 35
through Figure 26 on Page 37 describe Serial Port operations.
Table 28. Serial Ports—External Clock
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
3.0
3.0
ns
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
3.0
3.0
ns
tSDRE
Receive Data Setup Before RSCLKx
1
3.0
3.0
ns
tHDRE
Receive Data Hold After RSCLKx1
3.0
3.0
ns
tSCLKEW TSCLKx/RSCLKx Width
8.0
4.5
ns
tSCLKE
TSCLKx/RSCLKx Period
20.0
15.02
ns
tSUDTE Start-Up Delay From SPORT Enable To First External TFSx
3
4.0 × tSCLKE
4.0 × tSCLKE
ns
tSUDRE Start-Up Delay From SPORT Enable To First External RFSx
3
4.0 × tSCLKE
4.0 × tSCLKE
ns
Switching Characteristics
tDFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)4
10.0
10.0
ns
tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
1
0.0
0.0
ns
tDDTE
Transmit Data Delay After TSCLKx1
10.0
10.0
ns
tHDTE
Transmit Data Hold After TSCLKx
1
0.0
0.0
ns
1 Referenced to sample edge.
2 For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
3 Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
4 Referenced to drive edge.
Table 29. Serial Ports—Internal Clock
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
11.0
9.0
ns
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
2.0
2.0
ns
tSDRI
Receive Data Setup Before RSCLKx
1
9.5
9.0
ns
tHDRI
Receive Data Hold After RSCLKx
1
0.0
0.0
ns
Switching Characteristics
tDFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
3.0
3.0
ns
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
1
1.0
1.0
ns
tDDTI
Transmit Data Delay After TSCLKx
1
3.0
3.0
ns
tHDTI
Transmit Data Hold After TSCLKx
1
2.5
2.0
ns
tSCLKIW TSCLKx/RSCLKx Width
6.0
4.5
ns
1 Referenced to sample edge.
2 Referenced to drive edge.


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