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ADSP-BF533SBBC500 Datasheet(PDF) 32 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-BF533SBBC500 Datasheet(HTML) 32 Page - Analog Devices

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Rev. I
|
Page 32 of 64
|
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Parallel Peripheral Interface Timing
Table 27 and Figure 17 through Figure 22 describe parallel
peripheral interface operations.
Table 27. Parallel Peripheral Interface Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages
VDDEXT = 1.8 V
CSP_BGA Package
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tPCLKW PPI_CLK Width
8.0
8.0
6.0
ns
tPCLK
PPI_CLK Period1
20.0
20.0
15.0
ns
tSFSPE
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
6.0
6.0
4.0
2
ns
ns
tHFSPE
External Frame Sync Hold After PPI_CLK
1.02
1.02
1.02
ns
tSDRPE
Receive Data Setup Before PPI_CLK
3.5
3.5
3.5
ns
tHDRPE Receive Data Hold After PPI_CLK
1.5
1.5
1.5
ns
Switching Characteristics—GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
11.0
8.0
8.0
ns
tHOFSPE Internal Frame Sync Hold After PPI_CLK
1.7
1.7
1.7
ns
tDDTPE Transmit Data Delay After PPI_CLK
11.0
9.0
9.0
ns
tHDTPE Transmit Data Hold After PPI_CLK
1.8
1.8
1.8
ns
1 PPI_CLK frequency cannot exceed f
SCLK/2.
2 Applies when PPI_CONTROL Bit 8 is cleared. See Figure 19 and Figure 22.
Figure 17. PPI GP Rx Mode with Internal Frame Sync Timing
Figure 18. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
tHDRPE
tSDRPE
tHOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
tDFSPE
tPCLK
tPCLKW
tPCLK
tSFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
tHFSPE
tHDRPE
tSDRPE
tPCLKW


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