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ADSP-BF533SBBC500 Datasheet(PDF) 30 Page - Analog Devices

Part No. ADSP-BF533SBBC500
Description  Blackfin Embedded Processor
Download  64 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF533SBBC500 Datasheet(HTML) 30 Page - Analog Devices

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Rev. I
|
Page 30 of 64
|
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
SDRAM Interface Timing
Table 25. SDRAM Interface Timing1
1 SDRAM timing for TJ > 105°C is limited to 100 MHz.
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSSDAT
DATA Setup Before CLKOUT
2.1
1.5
ns
tHSDAT
DATA Hold After CLKOUT
0.8
0.8
ns
Switching Characteristics
tDCAD
Command, ADDR, Data Delay After CLKOUT
2
2 Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
6.0
4.0
ns
tHCAD
Command, ADDR, Data Hold After CLKOUT
2
1.0
1.0
ns
tDSDAT
Data Disable After CLKOUT
6.0
4.0
ns
tENSDAT
Data Enable After CLKOUT
1.0
1.0
ns
tSCLK
CLKOUT Period3
3 Refer to Table 13 on Page 21 for maximum fSCLK at various VDDINT.
10.0
7.5
ns
tSCLKH
CLKOUT Width High
2.5
2.5
ns
tSCLKL
CLKOUT Width Low
2.5
2.5
ns
Figure 15. SDRAM Interface Timing
tSCLK
CLKOUT
tSCLKL
tSCLKH
tSSDAT
tHSDAT
tENSDAT
tDCAD
tDSDAT
tHCAD
tDCAD
tHCAD
DATA (IN)
DATA (OUT)
COMMAND,
ADDRESS
(OUT)
NOTE: COMMAND =
SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.


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