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ADSP-BF533SBB500 Datasheet(PDF) 8 Page - Analog Devices

Part No. ADSP-BF533SBB500
Description  Blackfin Embedded Processor
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
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ADSP-BF533SBB500 Datasheet(HTML) 8 Page - Analog Devices

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Rev. I
Page 8 of 64
August 2013
• CEC interrupt pending register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but can be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 3.
• SIC interrupt mask register (SIC_IMASK) – This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in this register, that
peripheral event is unmasked and is processed by the sys-
tem when asserted. A cleared bit in this register masks the
peripheral event, preventing the processor from servicing
the event.
• SIC interrupt status register (SIC_ISR) – As multiple
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
• SIC interrupt wakeup enable register (SIC_IWR) – By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. See Dynamic
Power Management on Page 11.
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the
general-purpose interrupt to the IPEND output asserted is three
core clock cycles; however, the latency can be much higher,
depending on the activity within and the state of the processor.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors have
multiple, independent DMA channels that support automated
data transfers with minimal overhead for the processor core.
DMA transfers can occur between the processor’s internal
memories and any of its DMA-capable peripherals. Addition-
ally, DMA transfers can be accomplished between any of the
DMA-capable peripherals and external devices connected to the
external memory interfaces, including the SDRAM controller
and the asynchronous memory controller. DMA-capable
peripherals include the SPORTs, SPI port, UART, and PPI. Each
individual DMA-capable peripheral has at least one dedicated
DMA channel.
The DMA controller supports both 1-dimensional (1-D) and 2-
dimensional (2-D) DMA transfers. DMA transfer initialization
can be implemented from registers or from sets of parameters
called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
de-interleaved on the fly.
Examples of DMA types supported by the DMA controller
• A single, linear buffer that stops upon completion
• A circular, autorefreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
two pairs of memory DMA channels provided for transfers
between the various memories of the processor system. This
enables transfers of blocks of data between any of the memo-
ries—including external SDRAM, ROM, SRAM, and flash
memory—with minimal processor intervention. Memory DMA
transfers can be controlled by a very flexible descriptor-based
methodology or by a standard register-based autobuffer
The processor real-time clock (RTC) provides a robust set of
digital watch features, including current time, stopwatch, and
alarm. The RTC is clocked by a 32.768 kHz crystal external to
the ADSP-BF531/ADSP-BF532/ADSP-BF533 processors. The
RTC peripheral has dedicated power supply pins so that it can
remain powered up and clocked even when the rest of the pro-
cessor is in a low power state. The RTC provides several
programmable interrupt options, including interrupt per sec-
ond, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60 second counter, a 60 minute counter, a
24 hour counter, and a 32,768 day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. The two alarms are time of day and a day
and time of that day.

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