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ADSP-BF533SBB500 Datasheet(PDF) 41 Page - Analog Devices

Part No. ADSP-BF533SBB500
Description  Blackfin Embedded Processor
Download  64 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF533SBB500 Datasheet(HTML) 41 Page - Analog Devices

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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I
|
Page 41 of 64
|
August 2013
Timer Clock Timing
Table 35 and Figure 30 describe timer clock timing.
Timer Cycle Timing
Table 36 and Figure 31 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 35. Timer Clock Timing
Parameter
Min
Max
Unit
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
12
ns
Figure 30. Timer Clock Timing
PPI_CLK
TMRx OUTPUT
tTODP
Table 36. Timer Cycle Timing
VDDEXT = 1.8 V
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Characteristics
tWL Timer Pulse Width Low
1
1 × tSCLK
1 × tSCLK
ns
tWH Timer Pulse Width High
1
1 × tSCLK
1 × tSCLK
ns
tTIS Timer Input Setup Time Before CLKOUT Low
2
8.0
6.5
ns
tTIH Timer Input Hold Time After CLKOUT Low
2
1.5
1.5
ns
Switching Characteristics
tHTO Timer Pulse Width Output
1 × tSCLK
(2
32–1) × t
SCLK
1 × tSCLK
(2
32–1) × t
SCLK
ns
tTOD Timer Output Update Delay After CLKOUT High
7.5
6.5
ns
1 The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 31. Timer PWM_OUT Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
tTIS
tTIH
tWH,tWL
tTOD
tHTO


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