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ADSP-BF533SBB500 Datasheet(PDF) 38 Page - Analog Devices

Part No. ADSP-BF533SBB500
Description  Blackfin Embedded Processor
Download  64 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF533SBB500 Datasheet(HTML) 38 Page - Analog Devices

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Rev. I
|
Page 38 of 64
|
August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port—Master Timing
Table 32. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages
VDDEXT = 1.8 V
CSP_BGA Package
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tSSPIDM
Data Input Valid to SCK Edge (Data Input Setup) 10.5
9
7.5
ns
tHSPIDM SCK Sampling Edge to Data Input Invalid
–1.5
–1.5
–1.5
ns
Switching Characteristics
tSDSCIM SPISELx Low to First SCK Edge
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tSPICHM Serial Clock High Period
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tSPICLM
Serial Clock Low Period
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tSPICLK
Serial Clock Period
4 × tSCLK – 1.5
4 × tSCLK – 1.5
4 × tSCLK – 1.5
ns
tHDSM
Last SCK Edge to SPISELx High
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tSPITDM
Sequential Transfer Delay
2 × tSCLK – 1.5
2 × tSCLK – 1.5
2 × tSCLK – 1.5
ns
tDDSPIDM SCK Edge to Data Out Valid (Data Out Delay)
6
6
6
ns
tHDSPIDM SCK Edge to Data Out Invalid (Data Out Hold)
–1.0
–1.0
–1.0
ns
Figure 27. Serial Peripheral Interface (SPI) Port—Master Timing
tSDSCIM
tSPICLK
tHDSM
tSPITDM
tSPICLM
tSPICHM
tHDSPIDM
tHSPIDM
tSSPIDM
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
CPHA = 1
CPHA = 0
tDDSPIDM
tHSPIDM
tSSPIDM
tHDSPIDM
tDDSPIDM


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