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ADSP-BF533SBB500 Datasheet(PDF) 31 Page - Analog Devices

Part No. ADSP-BF533SBB500
Description  Blackfin Embedded Processor
Download  64 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF533SBB500 Datasheet(HTML) 31 Page - Analog Devices

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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I
|
Page 31 of 64
|
August 2013
External Port Bus Request and Grant Cycle Timing
Table 26 and Figure 16 describe external port bus request and
bus grant operations.
Table 26. External Port Bus Request and Grant Cycle Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages
VDDEXT = 1.8 V
CSP_BGA Package
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tBS BR Asserted to CLKOUT High Setup
4.6
4.6
4.6
ns
tBH CLKOUT High to BR Deasserted Hold Time
1.0
1.0
0.0
ns
Switching Characteristics
tSD CLKOUT Low to AMSx, Address, and ARE/AWE Disable
4.5
4.5
4.5
ns
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
4.5
4.5
4.5
ns
tDBG CLKOUT High to BG High Setup
6.0
5.5
3.6
ns
tEBG CLKOUT High to BG Deasserted Hold Time
6.0
4.6
3.6
ns
tDBH CLKOUT High to BGH High Setup
6.0
5.5
3.6
ns
tEBH CLKOUT High to BGH Deasserted Hold Time
6.0
4.6
3.6
ns
Figure 16. External Port Bus Request and Grant Cycle Timing
AMSx
CLKOUT
BG
BGH
BR
ADDR 19-1
ABE1-0
tBH
tBS
tSD
tSE
tSD
tSD
tSE
tSE
t
EBG
tDBG
t
EBH
tDBH
AWE
ARE


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