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ADSP-BF533SBB500 Datasheet(PDF) 27 Page - Analog Devices

Part No. ADSP-BF533SBB500
Description  Blackfin Embedded Processor
Download  64 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF533SBB500 Datasheet(HTML) 27 Page - Analog Devices

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ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I
|
Page 27 of 64
|
August 2013
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 21 and Figure 11 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 25, combinations of
CLKIN and clock multipliers/divisors must not result in core/
system clocks exceeding the maximum limits allowed for the
processor, including system clock restrictions related to supply
voltage.
Table 21. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period
1, 2, 3, 4
25.0
100.0
ns
tCKINL
CLKIN Low Pulse
10.0
ns
tCKINH
CLKIN High Pulse
10.0
ns
tWRST
RESET Asserted Pulse Width Low5
11
 t
CKIN
ns
tNOBOOT
RESET Deassertion to First External Access Delay6
3
 t
CKIN
5
 t
CKIN
ns
1 Applies to PLL bypass mode and PLL non bypass mode.
2 CLKIN frequency must not change on the fly.
3 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 11 on Page 21 through
Table 13 on Page 21. Since the default behavior of the PLL is to multiply the CLKIN frequency by 10, the 400 MHz speed grade parts cannot use the full CLKIN period range.
4 If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5 Applies after power-up sequence is complete. See Table 22 and Figure 12 for power-up reset timing.
6 Applies when processor is configured in No Boot Mode (BMODE1-0 = b#00).
Figure 11. Clock and Reset Timing
Table 22. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirement
tRST_IN_PWR
RESET Deasserted After the VDDINT, VDDEXT, VDDRTC, and CLKIN Pins Are Stable and
Within Specification
3500
 t
CKIN
ns
In Figure 12, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC
Figure 12. Power-Up Reset Timing
CLKIN
tWRST
tCKIN
tCKINL
tCKINH
RESET
tNOBOOT
RESET
tRST_IN_PWR
CLKIN
V
DD_SUPPLIES


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