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ADN2850BRUZ25 Datasheet(PDF) 15 Page - Analog Devices

Part No. ADN2850BRUZ25
Description  Nonvolatile Memory, Dual 1024-Position Digital Resistor
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ADN2850BRUZ25 Datasheet(HTML) 15 Page - Analog Devices

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Data Sheet
ADN2850
Rev. E | Page 15 of 28
resistor and the capacitive loading at the SDO-to-SDI interface may
require additional time delay between subsequent devices.
When two ADN2850s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep
AA
CSEE
AA
low until all 48 bits are
clocked into their respective serial registers.
AA
CSEE
AA
is then pulled
high to complete the operation.
CLK
RP
2.2k
SDI
SDO
U2
CS
CLK
SDI
SDO
U1
ADN2850
CS
VDD
SCLK SS
MOSI
MICRO-
CONTROLLER
ADN2850
Figure 28. Daisy-Chain Configuration Using SDO
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the ADN2850
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal B, and
Terminal W that exceed VDD or VSS are clamped by the internal
forward-biased diodes (see Figure 29).
VSS
VDD
W
B
Figure 29. Maximum Terminal Voltages Set by VDD and VSS
The GND pin of the ADN2850 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the ADN2850 ground terminal should be joined remotely to
the common ground (see Figure 30). The digital input control
signals to the ADN2850 must be referenced to the device
ground pin (GND) and must satisfy the logic level defined in
the Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
extends from VSS to VDD, regardless of the digital input level.
Power-Up Sequence
Because there are diodes to limit the voltage compliance at
Terminal B, and Terminal W (see Figure 29), it is important to
power VDD and VSS first before applying any voltage to Terminal
B, and Terminal W. Otherwise, the diode is forward-biased such
that VDD and VSS are powered unintentionally. For example,
applying 5 V across Terminal W and Terminal B prior to VDD
causes the VDD terminal to exhibit 4.3 V. It is not destructive to
the device, but it might affect the rest of the user’s system. The
ideal power-up sequence is GND, VDD and VSS, digital inputs,
and VB, and VW. The order of powering VB, VW, and the digital
inputs is not important as long as they are powered after VDD
and VSS.
Regardless of the power-up sequence and the ramp rates of the
power supplies, when VDD and VSS are powered, the power-on
preset activates, which restores the EEMEM values to the RDAC
registers.
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 µF to 0.1 µF disk or chip ceramic capacitors.
Also, apply low ESR, 1 µF to 10 µF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 30).
ADN2850
VDD
GND
VSS
C3
10µF
C4
10µF
C2
0.1µF
C1
0.1µF
+
+
VDD
VSS
Figure 30. Power Supply Bypassing


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