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ADN2850BRUZ25 Datasheet(PDF) 8 Page - Analog Devices |
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ADN2850BRUZ25 Datasheet(HTML) 8 Page - Analog Devices |
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8 / 28 page 
ADN2850 Data Sheet Rev. E | Page 8 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SDI SDO GND V1 VSS W1 CLK B1 CS PR WP VDD V2 W2 B2 RDY 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ADN2850 TOP VIEW (Not to Scale) Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges. 2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first. 3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed. 4 GND Ground Pin, Logic Ground Reference. 5 VSS Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual supply, it must be able to sink 2 mA for 15 ms when storing data to EEMEM. 6 V1 Log Output Voltage 1. Generates voltage from an internal diode configured transistor. 7 W1 Wiper Terminal of RDAC1. ADDR (RDAC1) = 0x0. 8 B1 Terminal B of RDAC1. 9 B2 Terminal B of RDAC2. 10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1. 11 V2 Log Output Voltage 2. Generates voltage from an internal diode configured transistor. 12 VDD Positive Power Supply. 13 AA WPEE Optional Write Protect. When active low, AA WPEE AA prevents any changes to the present contents, except AA PREE AA strobe. CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie AA WPEE AA to VDD, if not used. 14 AA PREE Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. AA PREE AA is activated at the logic high transition. Tie AA PREE AA to VDD, if not used. 15 AA CSEE Serial Register Chip Select Active Low. Serial register operation takes place when AA CSEE AA returns to logic high. 16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and AA PREE AA . |
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