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ADN2850BRUZ25 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADN2850BRUZ25
Description  Nonvolatile Memory, Dual 1024-Position Digital Resistor
Download  28 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADN2850BRUZ25 Datasheet(HTML) 5 Page - Analog Devices

 
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Data Sheet
ADN2850
Rev. E | Page 5 of 28
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 3 V and VDD = 5 V.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Clock Cycle Time (tCYC)
t1
20
ns
EE
AA
Setup Time
CS
t2
10
ns
CLK Shutdown Time to
AA
CSEE
AA
Rise
t3
1
tCYC
Input Clock Pulse Width
t4, t5
Clock level high or low
10
ns
Data Setup Time
t6
From positive CLK transition
5
ns
Data Hold Time
t7
From positive CLK transition
5
ns
AA
CSEE
AA
to SDO-SPI Line Acquire
t8
40
ns
AA
CSEE
AA
to SDO-SPI Line Release
t9
50
ns
CLK to SDO Propagation Delay
10F
2
t10
RP = 2.2 kΩ, CL < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 kΩ, CL < 20 pF
0
ns
AA
CSEE
AA
High Pulse Width
11F
3
t12
10
ns
AA
CS
EE
AA
High to
AA
CSEE
AA
High3
t13
4
tCYC
RDY Rise to
AA
CSEE
AA
Fall
t14
0
ns
AA
CSEE
AA
Rise to RDY Fall Time
t15
0.15
0.3
ms
Store EEMEM Time
12F
4,
13F
5
t16
Applies to instructions 0x2, 0x3
15
50
ms
Read EEMEM Time4
t16
Applies to instructions 0x8, 0x9, 0x10
7
30
µs
AA
CSEE
AA
Rise to Clock Rise/Fall Setup
t17
10
ns
Preset Pulse Width (Asynchronous)
14F
6
tPRW
50
ns
Preset Response Time to Wiper Setting6
tPRESP
AA
PREE
AA
pulsed low to refresh wiper positions
30
µs
Power-On EEMEM Restore Time6
tEEMEM
30
µs
FLASH/EE MEMORY RELIABILITY
Endurance
15F
7
TA = 25°C
1
MCycles
100
kCycles
Data Retention
16F
8
100
Years
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3
Valid for commands that do not activate the RDY pin.
4
RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs;
CMD_2, CMD_3 ~ 15 ms, PR hardware pulse ~ 30 µs.
5
Store EEMEM time depends on the temperature and EEMEM write cycles. Higher timing is expected at lower temperature and higher write cycles.
6
Not shown in Figure 2 and Figure 3.
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.


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