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SSTV16857 Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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SSTV16857 Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 7 page 5 www.fairchildsemi.com AC Electrical Characteristics (SSTV16857) (Note 4) Note 4: Refer to Figure 1 through Figure 7. Note 5: This parameter is not production tested. Note 6: For data signal input slew rate t 1 V/ns. Note 7: For data signal input slew rate t 0.5 V/ns and 1 V/ns. Note 8: For CK, CK signals input slew rates are t 1 V/ns. AC Electrical Characteristics (SSTVN16857) (Note 9) Note 9: Refer to Figure 1 through Figure 7. Note 10: This parameter is not production tested. Note 11: For data signal input slew rate t 1 V/ns. Note 12: For data signal input slew rate t 0.5 V/ns and 1 V/ns. Note 13: For CK, CK signals input slew rates are t 1 V/ns. Note 14: Simultaneous Switching is guaranteed by characterization. Symbol Parameter TA 0qC to 70qC, CL 30 pF, RL 50: Units VDD 2.5V r 0.2V; VDDQ 2.5V r 0.2V Min Max fMAX Maximum Clock Frequency 200 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, 22 ns (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) tINACT Differential Inputs De-activation Time, 22 ns (Note 5) data and clock inputs must be held at valid levels (not floating) after RESET LOW tS Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5) 0.65 ns Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 tH Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5) 0.75 ns Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 ns tPHL, tPLH Propagation Delay CLK, CLK to Qn (Figure 4) 1.1 2.8 ns tPHL Propagation Delay RESET to Qn (Figure 6) 5.0 ns tSK(Pn-Pn) Output to Output Skew 200 ps Symbol Parameter TA 0qC to 70qC, CL 30 pF, RL 50: Units VDD 2.5V r 0.2V; VDDQ 2.5V r 0.2V Min Max fMAX Maximum Clock Frequency 220 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, 22 ns (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) tINACT Differential Inputs De-activation Time, 22 ns (Note 5) Data and Clock Inputs must be held at valid levels (not floating) after RESET LOW tS Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5) 0.65 ns Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) 0.75 tH Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5) 0.75 ns Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 ns tPHL, tPLH Propagation Delay CLK, CLK to Qn (Figure 4) 1.1 2.4 ns tPSS Propagation Delay Simultaneous Switching CLK, CLK to Qn (Note 14) 2.7 ns tPHL Propagation Delay RESET to Qn (Figure 6) 5.0 ns tSK(Pn-Pn) Output to Output Skew 200 ps |
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