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LT8705 Datasheet(PDF) 10 Page - Linear Technology |
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LT8705 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 30 page  LTC3780 10 3780ff For more information www.linear.com/LTC3780 PGOOD (Pin 1/Pin 30): Open-Drain Logic Output. PGOOD is pulled to ground when the output voltage is not within ±7.5% of the regulation point. SS (Pin 2/Pin 31): Soft-start reduces the input power sources’ surge currents by gradually increasing the controller’s current limit. A minimum value of 6.8nF is recommended on this pin. SENSE+ (Pin 3/Pin 1): The (+) Input to the Current Sense and Reverse Current Detect Comparators. The ITHpinvolt- ageandbuilt-inoffsetsbetweenSENSE–andSENSE+pins, in conjunction with RSENSE, set the current trip threshold. SENSE– (Pin 4/Pin 2): The (–) Input to the Current Sense and Reverse Current Detect Comparators. ITH (Pin 5/Pin 3): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V. VOSENSE (Pin 6/Pin 4): Error Amplifier Feedback Input. This pin connects the error amplifier input to an external resistor divider from VOUT. SGND(Pin7/Pin5,ExposedPadPin33):SignalGround.All small-signal components and compensation components shouldconnecttothisground,whichshouldbeconnected to PGND at a single point. The QFN exposed pad must be soldered to PCB ground for electrical connection and rated thermal performance. RUN (Pin 8/Pin 6): Run Control Input. Forcing the RUN pin below 1.5V causes the IC to shut down the switching regulator circuitry. There is a 100k resistor between the RUN pin and SGND in the IC. Do not apply >6V to this pin. FCB (Pin 9/Pin 7): Forced Continuous Control Input. The voltage applied to this pin sets the operating mode of the controller. When the applied voltage is less than 0.8V, the forced continuous current mode is active. When this pin is allowed to float, the Burst Mode operation is active in boost operation and the skip-cycle mode is active in buck operation. When the pin is tied to INTVCC, the constant frequency discontinuous current mode is active in buck or boost operation. PLLFLTR (Pin 10/Pin 8): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. PLLIN (Pin 11/Pin 10): External Synchronization Input to Phase Detector. This pin is internally terminated to SGND with 50kΩ. The phase-locked loop will force the rising bottom gate signal of the controller to be synchronized with the rising edge of the PLLIN signal. STBYMD (Pin 12/Pin 11): LDO Control Pin. Determines whether the internal LDO remains active when the control- ler is shut down. See Operation section for details. If the STBYMD pin is pulled to ground, the SS pin is internally pulled to ground, preventing start-up and thereby provid- ing a single control pin for turning off the controller. To keep the LDO active when RUN is low, for example to power a “wake up” circuit which controls the state of the RUN pin, bypass STBYMD to signal ground with a 0.1µF capacitor, or use a resistor divider from VIN to keep the pin within 2V to 5V. BOOST2, BOOST1 (Pins 13, 24/Pins 14, 27): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitorCAandCB(Figure11)connectshere.TheBOOST2 pin swings from a diode voltage below INTVCC up to VIN + INTVCC. The BOOST1 pin swings from a diode voltage below INTVCC up to VOUT + INTVCC. TG2,TG1(Pins14,23/Pins15,26):TopGateDrive.Drives the top N-channel MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. SW2,SW1(Pins15,22/Pins17,24):SwitchNode.The(–) terminal of the bootstrap capacitor CA and CB (Figure 11) connects here. The SW2 pin swings from a Schottky diode (external) voltage drop below ground up to VIN. The SW1 pin swings from a Schottky diode (external) voltage drop below ground up to VOUT. pin FuncTions (SSOP/QFN) |
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