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SPT8100 Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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SPT8100 Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 10 page SPT8100 16-BIT, 5 MSPS CMOS A/D CONVERTER TECHNICAL DATA JANUARY 9, 2002 FEATURES • 16-bit, 5 MSPS CMOS analog-to-digital converter • On-chip PGA: gain range from 0 to 19.5 dB in seven selectable settings: 0 dB, +2.9 dB, +5.8 dB, +11.8 dB, +14.8 dB, +17.5 dB, +19.5 dB • DLE: ±0.5 LSB, ILE: ±1.25 LSB • SFDR: 94 dB @ ƒIN = 900 kHz, –8.1 dBFS • Internal sample-and-hold and voltage reference • Power dissipation: 465 mW at 5 MSPS • +5 V analog supply and +3.3 to +5.25 V digital output supply • 44-lead LQFP plastic package APPLICATIONS • Data acquisition systems • IR imaging • Scanners and digital copiers • High-end CCD cameras • Medical imaging • Wireless communications • Lab and test equipment • Automatic test equipment DESCRIPTION The SPT8100 is a high-performance, 16-bit analog-to- digital converter that operates at a sample rate of up to 5 MSPS. Excellent dynamic performance and high linear- ity is achieved by a digitally calibrated pipelined architec- ture fabricated in CMOS process technology. A low-noise programmable gain amplifier (PGA) is also in- corporated on chip. The PGA is digitally programmable in seven selected settings over a 0 to +19.5 dB range. The SPT8100 also features an on-chip internal sample-and- hold and internal reference for minimal external circuitry. It operates from a single +5 V supply. Total power dissipa- tion, including internal reference, is 465 mW. A separate digital output supply pin is provided for +3.3 V or 5 V logic output levels. The SPT8100 is available in a 44-lead LQFP package over the industrial temperature range of –40 °C to +85 °C. AGND Low-Noise PGA 16-bit, 5 MSPS ADC VREF GS2 – GS0 (Gain Set) VIN+ VIN– 16-bits D15 – D0 (Data Outputs) OVR (Over-Range) DVDD +5V OVDD +3/5 V BIASR (Ext Bias Resistor) CLK VCM OE (Output Enable) BIASC (Ext Bias Capacitor) RDY (Ready) AVDD +5V OGND DGND RS (Reset) VRT VRB BLOCK DIAGRAM |
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