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LT1720IDD Datasheet(PDF) 13 Page - Linear Technology

Part # LT1720IDD
Description  UltraFast:4.5ns at 20mV Overdrive 7ns at 5mV Overdrive
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT1720IDD Datasheet(HTML) 13 Page - Linear Technology

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LT1720/LT1721
13
17201fc
Circuit Description
The block diagram of one comparator in the LT1720/LT1721
is shown in Figure 6. There are differential inputs (+IN/–IN),
an output (OUT), a single positive supply (VCC) and ground
(GND). All comparators are completely independent, shar-
ing only the power and ground pins. The circuit topology
consists of a differential input stage, a gain stage with
hysteresis and a complementary common-emitter output
stage. All of the internal signal paths utilize low voltage
swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complex-
ity and die area of two complete input stages such as
are found in rail-to-rail input comparators. With a 2.7V
supply, the LT1720/LT1721 still have a respectable 1.6V
of input common mode range. The differential input volt-
age range is rail-to-rail, without the large input currents
found in competing devices. The input stage also features
phase reversal protection to prevent false outputs when
the inputs are driven below the –100mV common mode
voltage limit.
The internal hysteresis is implemented by positive, nonlin-
ear feedback around a second gain stage. Until this point,
the signal path has been entirely differential. The signal
path is then split into two drive signals for the upper and
lower output transistors. The output transistors are con-
nected common emitter for rail-to-rail output operation.
The Schottky clamps limit the output voltages at about
300mV from the rail, not quite the 50mV or 15mV of Linear
APPLICATIONS INFORMATION
Technology’s rail-to-rail amplifiers and other products. But
the output of a comparator is digital, and this output stage
can drive TTL or CMOS directly. It can also drive ECL, as
described earlier, or analog loads as demonstrated in the
applications to follow.
The bias conditions and signal swings in the output stages
are designed to turn their respective output transistors off
faster than on. This nearly eliminates the surge of current
from VCC to ground that occurs at transitions, keeping
the power consumption low even with high output-toggle
frequencies.
The low surge current is what keeps the power consump-
tion low at high output-toggle frequencies. The frequency
dependence of the supply current is shown in the Typical
Performance Characteristics. Just 20pF of capacitive load
on the output more than triples the frequency dependent
rise. The slope of the no-load curve is just 32μA/MHz. With
a 5V supply, this current is the equivalent of charging and
discharging just 6.5pF. The slope of the 20pF load curve is
133μA/MHz, an addition of 101μA/MHz, or 20μA/MHz-V,
units that are equivalent to picoFarads.
The LT1720/LT1721 dynamic current can be estimated
by adding the external capacitive loading to an internal
equivalent capacitance of 5pF to 15pF, multiplied by the
toggle frequency and the supply voltage. Because the
capacitance of routing traces can easily approach these
values, the dynamic current is dominated by the load in
most circuits.
Figure 6. LT1720/LT1721 Block Diagram
+
+
+
+
+IN
–IN
AV1
AV2
NONLINEAR STAGE
OUT
GND
17201 F06
VCC
+
+


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