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LT1720IDD Datasheet(PDF) 11 Page - Linear Technology

Part # LT1720IDD
Description  UltraFast:4.5ns at 20mV Overdrive 7ns at 5mV Overdrive
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LT1720IDD Datasheet(HTML) 11 Page - Linear Technology

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LT1720/LT1721
11
17201fc
Interfacing the LT1720/LT1721 to ECL
The LT1720/LT1721 comparators can be used in high
speed applications where Emitter-Coupled Logic (ECL) is
deployed. To interface the outputs of the LT1720/LT1721
to ECL logic inputs, standard TTL/CMOS to ECL level
translators such as the 10H124, 10H424 and 100124
can be used. These components come at a cost of a few
nanoseconds additional delay as well as supply currents
of 50mA or more, and are only available in quads. A faster,
simpler and lower power translator can be constructed
with resistors as shown in Figure 5.
Figure 5a shows the standard TTL to Positive ECL (PECL)
resistive level translator. This translator cannot be used for
the LT1720/LT1721, or with CMOS logic, because it depends
on the 820Ω resistor to limit the output swing (VOH) of
the all-NPN TTL gate with its so-called totem-pole output.
The LT1720/LT1721 are fabricated in a complementary
bipolar process and their output stage has a PNP driver
that pulls the output nearly all the way to the supply rail,
even when sourcing 10mA.
Figure 5b shows a three resistor level translator for interfac-
ing the LT1720/LT1721 to ECL running off the same supply
rail. No pull-down on the output of the LT1720/LT1721
is needed, but pull-down R3 limits the VIH seen by the
PECL gate. This is needed because ECL inputs have both
a minimum and maximum VIH specification for proper
operation. Resistor values are given for both ECL interface
types; in both cases it is assumed that the LT1720/LT1721
operates from the same supply rail.
Figure 5c shows the case of translating to PECL from an
LT1720/LT1721 powered by a 3V supply rail. Again, resis-
tor values are given for both ECL interface types. This time
four resistors are needed, although with 10KH/E, R3 is not
needed. In that case, the circuit resembles the standard TTL
translator of Figure 5a, but the function of the new resistor,
R4, is much different. R4 loads the LT1720/LT1721 output
when high so that the current flowing through R1 doesn’t
forwardbiastheLT1720/LT1721’sinternalESDclampdiode.
Although this diode can handle 20mA without damage,
normal operation and performance of the output stage can
be impaired above 100μA of forward current. R4 prevents
this with the minimum additional power dissipation.
APPLICATIONS INFORMATION
Finally, Figure 5d shows the case of driving standard, nega-
tive-rail, ECL with the LT1720/LT1721. Resistor values are
given for both ECL interface types and for both a 5V and 3V
LT1720/LT1721 supply rail. Again, a fourth resistor, R4 is
needed to prevent the low state current from flowing out of
the LT1720/LT1721, turning on the internal ESD/substrate
diodes. Not only can the output stage functionality and
speed suffer, but in this case the substrate is common to
all the comparators in the LT1720/LT1721, so operation
of the other comparator(s) in the same package could
also be affected. Resistor R4 again prevents this with the
minimum additional power dissipation.
For all the dividers shown, the output impedance is about
110Ω. This makes these fast, less than a nanosecond,
with most layouts. Avoid the temptation to use speedup
capacitors. Not only can they foul up the operation of
the ECL gate because of overshoots, they can damage
the ECL inputs, particularly during power-up of separate
supply configurations.
The level translator designs assume one gate load. Multiple
gates can have significant IIH loading, and the transmis-
sion line routing and termination issues also make this
case difficult.
ECL, and particularly PECL, is valuable technology for high
speed system design, but it must be used with care. With
less than a volt of swing, the noise margins need to be
evaluated carefully. Note that there is some degradation of
noise margin due to the
±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of the
logic levels, whereas the LT1720/LT1721 and the circuits
shown give levels that are stable with temperature. This
will degrade the noise margin over temperature. In some
configurations it is possible to add compensation with
diode or transistor junctions in series with the resistors
of these networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from ON
Semiconductor (www.onsemi.com).


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