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SPT7871SIQ Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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SPT7871SIQ Datasheet(HTML) 7 Page - Fairchild Semiconductor |
7 / 8 page 7 9/7/98 SPT7871 PACKAGE OUTLINE adequate thermal performance under laboratory tests. Air flow may be required for operation at elevated ambient temperature. Fairchild recommends that the junction tem- perature be maintained under +150 °C. The thermal impedance values for the cerquad package are θJC = 3.3 °C/W and θJA = 70 °C/W (junction to ambient in still air with no heat sink). TTL DIGITAL OUTPUT LEVELS The SPT7871 supports TTL and some CMOS logic levels. (Refer to minimum high voltage level for selected digital parts that will interface with the SPT7871.) It has single-ended outputs that are driven off a separate +5 V digital supply (DVCC). THERMAL MANAGEMENT Fairchild recommends that a heat sink be used for this device to ensure rated performance. A heat sink in still air provides Figure 4 - Digital Outputs Equivalent Circuit Figure 2 - Typical Interface Circuit Figure 3 - Clock Input Equivalent Circuit AGND CLK 26 k Ω AVCC VEE 6 k Ω 52 k Ω -1.3 V (ESD) (ESD) NCLK 26 k Ω (ESD) (ESD) DGND (ESD) (ESD) TTL OUT DVCC +A5 -A5.2 .01 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 DGND .01 FB1 Analog Input ECL Differential Clock Input .01 .01 MINV LINV +A5 +D5 Interfacing Logics SPT7871 AGND VEE AVCC CLK CLK VB VT VM VIN X X DVCC FB2 FB3 * * Notes: 1) = Line termination 2) = 0.01 µF chip cap. in parallel with 2.2 µF, tant cap. 3) Immediate output buffer is highly recommended to optimize the performance due to reflection. X * +5V DGND +D5 + 10 µF +5 V -5.2 V AGND +A5 -A5.2 + 10 µF + 10µF 44L Cerquad C D A B A B 0 - 5° E F G H 1 44 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.550 typ 13.97 typ B 0.685 0.709 17.40 18.00 C 0.037 0.041 0.94 1.04 D 0.016 typ 0.41 typ E 0.008 typ 0.20 typ F 0.027 0.051 0.69 1.30 G 0.006 typ 0.15 typ H 0.080 0.150 2.03 3.81 |
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