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TLC7524CNE4 Datasheet(PDF) 6 Page - Texas Instruments

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Part No. TLC7524CNE4
Description  8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TLC7524CNE4 Datasheet(HTML) 6 Page - Texas Instruments

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TLC7524C, TLC7524E, TLC7524I
8BIT MULTIPLYING DIGITALTOANALOG CONVERTERS
SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder,
analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2
bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order
bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted
current sources. Most applications only require the addition of an external operational amplifier and a voltage
reference.
The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference
current, Iref, is switched to OUT2. The current source I/256 represents the constant current flowing through the
termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the
substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all
digital inputs high, the off-state switch capacitance (30pF maximum) appears at OUT2 and the on-state switch
capacitance (120pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown
in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would
be switched to OUT1.
The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control
signals. When CS and WR are both low, analog output on these devices responds to the data activity on the
DB0−DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the
analog output. When either the CS signal or WR signal goes high, the data on the DB0−DB7 inputs are latched
until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state
of the WR signal.
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input
coding for unipolar and bipolar operation respectively.
Iref
REF
OUT2
OUT1
RFB
R
120 pF
30 pF
IIkg
I/256
IIkg
Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low


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