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TLC7524IDR Datasheet(PDF) 3 Page - Texas Instruments |
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TLC7524IDR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 21 page  TLC7524C, TLC7524E, TLC7524I 8BIT MULTIPLYING DIGITALTOANALOG CONVERTERS SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions VDD = 5V VDD = 15V UNIT MIN NOM MAX MIN NOM MAX UNIT Supply voltage, VDD 4.75 5 5.25 14.5 15 15.5 V Reference voltage, Vref ±10 ±10 V High-level input voltage, VIH 2.4 13.5 V Low-level input voltage, VIL 0.8 1.5 V CS setup time, tsu(CS) 40 40 ns CS hold time, th(CS) 0 0 ns Data bus input setup time, tsu(D) 25 25 ns Data bus input hold time, th(D) 10 10 ns Pulse duration, WR low, tw(WR) 40 40 ns TLC7524C 0 +70 0 +70 Operating free-air temperature, TA TLC7524I −25 +85 −25 +85 °C Operating free-air temperature, TA TLC7524E −40 +85 −40 +85 C electrical characteristics over recommended operating free-air temperature range, Vref = ±10V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5V VDD = 15V UNIT PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT IIH High-level input current VI = VDD 10 10 µA IIL Low-level input current VI = 0 −10 −10 µA IIkg Output leakage OUT1 DB0−DB7 at 0V, Vref = ± 10V WR, CS at 0V, ±400 ±200 nA IIkg Output leakage current OUT2 DB0−DB7 at VDD, Vref = ± 10V WR, CS at 0V, ±400 ±200 nA IDD Supply current Quiescent DB0−DB7 at VIHmin or VILmax 1 2 mA IDD Supply current Standby DB0−DB7 at 0V or VDD 500 500 µA kSVS Supply voltage sensitivity, ∆gain/∆VDD ∆VDD = ±10% 0.01 0.16 0.005 0.04 %FSR/% Ci Input capacitance, DB0−DB7, WR, CS VI = 0 5 5 pF OUT1 DB0−DB7 at 0V, WR, CS at 0V 30 30 Co Output capacitance OUT2 DB0−DB7 at 0V, WR, CS at 0V 120 120 pF Co Output capacitance OUT1 DB0−DB7 at VDD, WR, CS at 0V 120 120 pF OUT2 DB0−DB7 at VDD, WR, CS at 0V 30 30 Reference input impedance (REF to GND) 5 20 5 20 k Ω |
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