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SPT7610 Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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SPT7610 Datasheet(HTML) 5 Page - Fairchild Semiconductor |
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5 / 10 page  5 1/21/02 SPT7610 Figure 1 – Timing Diagram 2 FIRST RISING EDGE POWER ON 8 OUTPUT BANK A (DA0-6) OUTPUT BANK B (DB0-6) DRA CLK IN DRB VIN NDRA NDRB TEST 3 5 4 2 1 6 INVALID DATA 1 ADC (Normal Operation) 9 10 11 8 TEST MODE 7 tsu tdr tod tdr tod ADC (Normal Operation) INVALID DATA INVALID DATA INVALID DATA 7 9 Bank A Test Pattern 1: - Even Bits = Hi - Odd Bits = Low Bank B Test Pattern 1: - Even Bits = Hi - Odd Bits = Low Bank A Test Pattern 2: - Even Bits = Low - Odd Bits = Hi Bank B Test Pattern 2: - Even Bits = Low - Odd Bits = Hi LOGIC LOW Figure 2 – Test Mode Timing Diagram CLK (1 GHz) DRA DRA Data Bank A DRB DRB Data Bank B VIN N N+1 N+2 N+3 N+4 1 nsec todB tdrB tdrA N2 N todA N1 N3 OutputB Skew (toskB) N+1 N+2 DOBDRB Delay (todrB) OutputA Skew (toskA) DOADRA Delay (todrA) N+5 |
Similar Part No. - SPT7610 |
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Similar Description - SPT7610 |
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