TLV1572

2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS

SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN

SLAS171A – DECEMBER 1997– REVISED SEPTEMBER 1998

11

POST OFFICE BOX 655303

APPLICATION INFORMATION

interfacing TLV1572 to SPI/QSPI compatible microcontrollers(

µCs) (continued)

Unlike the DSP mode in which the conversion is initiated by the FS input signal from the DSP, the conversion

is initiated by the incoming SCLK after CS falls. Sampling of the input is started on the first rising edge of SCLK

after CS goes low. After six null bits, the A/D conversion data becomes available on SCLK rising edges and is

latched by the

µC on the falling edges. CS can be pulled high during the conversion before the LSB is shifted

out to use the device as a lower resolution ADC. Figure 9 shows the

µC mode timing diagram.

The device goes into autopower down after the LSB is shifted out and is brought out of powerdown by the next

clock rising edge as shown in Figure 9.

12

3

4

5

6

7

16

0

0

0

0

0

0

LSB (N)

SCLK

CS

FS

DO

MSB

12

3

4

5

6

7

16

0

0

0

0

0

Autopower Down

0

LSB(N+1)

Sampling

Conversion

Sample (N)

(N)

MSB(N+1)

Figure 9.

µC Application Timing Diagram

key points

1.

When CS goes low, if FS is high, it is in

the falling edge of CS and again on an internally delayed falling edge of CS. Only if both latches latch 1,

then

µC mode is set else DSP mode is set. Only polarity = 0 is supported, i.e. SCLK idles low. Only

clock_phase = 1 is supported as shown in the timing diagrams.

2.

For each conversion 16 clocks have to be supplied. If the

µC cannot take in 16 bits at a time, it may take

8 bits with 8 clocks and the next 8 bits with another 8 clocks keeping CS low throughout the conversion.

The delay between these two 8-clock periods must not be longer than 100

µs.

3.

Sampling starts on the first rising edge of SCLK and ends on the edge when the 6th 0 bit is sent out.

Decisions are made on the rising edge and data is output on the same edge but a bit delayed to avoid noise.

4.

The device goes into autopower down on the falling edge of the 16th clock and is brought out of powerdown

by next first (17th) clock rising edge.

5.

If the (Q)SPI wants less than a 16-bit transfer, CS must go high after each transfer. The falling edge of CS

resets the TLV1572 for the next conversion. Thus a 14-bit transfer is possible when using the device as an

8-bit A/D.

6.

CS going high puts the device in 3-state and complete powerdown. CS going low sets the mode and pulls

DO out of 3-state.