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PCF8576DU/2DA/2 Datasheet(PDF) 8 Page - NXP Semiconductors

Part # PCF8576DU/2DA/2
Description  Universal LCD driver for low multiplex rates
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8576DU/2DA/2 Datasheet(HTML) 8 Page - NXP Semiconductors

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PCF8576D
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 14 — 10 June 2013
8 of 57
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are to the power supplies
(VDD, VSS, and VLCD) and the LCD panel chosen for the application.
7.1 Power-On Reset (POR)
At power-on the PCF8576D resets to the following starting conditions:
All backplane and segment outputs are set to VLCD
The selected drive mode is: 1:4 multiplex with 13 bias
Blinking is switched off
Input and output bank selectors are reset
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E = 0, see Table 12)
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 12 bias voltage level for the 1:2 multiplex drive mode configuration is
selected. The LCD voltage can be temperature compensated externally using the supply
to pin VLCD.
The resistance of the power lines must be kept to a minimum.
For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line
must be routed separately between the chip and the connector.
Fig 5.
Typical system configuration
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
tr
2CB
SDA
SCL
OSC
40 segment drives
4 backplanes
LCD PANEL
(up to 160
elements)
PCF8576D
A0
A1
A2
SA0
VDD
VSS
VSS
VDD
VLCD
mdb079
R


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