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P6KE56AG Datasheet(PDF) 4 Page - ON Semiconductor |
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P6KE56AG Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 5 page P6KE6.8A Series http://onsemi.com 4 APPLICATION NOTES RESPONSE TIME In most applications, the transient suppressor device is placed in parallel with the equipment or component to be protected. In this situation, there is a time delay associated with the capacitance of the device and an overshoot condition associated with the inductance of the device and the inductance of the connection method. The capacitance effect is of minor importance in the parallel protection scheme because it only produces a time delay in the transition from the operating voltage to the clamp voltage as shown in Figure 7. The inductive effects in the device are due to actual turn-on time (time required for the device to go from zero current to full current) and lead inductance. This inductive effect produces an overshoot in the voltage across the equipment or component being protected as shown in Figure 8. Minimizing this overshoot is very important in the application, since the main purpose for adding a transient suppressor is to clamp voltage spikes. The P6KE6.8A series has very good response time, typically < 1 ns and negligible inductance. However, external inductive effects could produce unacceptable overshoot. Proper circuit layout, minimum lead lengths and placing the suppressor device as close as possible to the equipment or components to be protected will minimize this overshoot. Some input impedance represented by Zin is essential to prevent overstress of the protection device. This impedance should be as high as possible, without restricting the circuit operation. DUTY CYCLE DERATING The data of Figure 1 applies for non-repetitive conditions and at a lead temperature of 25 °C. If the duty cycle increases, the peak power must be reduced as indicated by the curves of Figure 6. Average power must be derated as the lead or ambient temperature rises above 25 °C. The average power derating curve normally given on data sheets may be normalized and used for this purpose. At first glance the derating curves of Figure 6 appear to be in error as the 10 ms pulse has a higher derating factor than the 10 ms pulse. However, when the derating factor for a given pulse of Figure 6 is multiplied by the peak power value of Figure 1 for the same pulse, the results follow the expected trend. TYPICAL PROTECTION CIRCUIT Vin VL V Vin Vin (TRANSIENT) VL td V VL Vin (TRANSIENT) Zin LOAD OVERSHOOT DUE TO INDUCTIVE EFFECTS tD = TIME DELAY DUE TO CAPACITIVE EFFECT t t Figure 7. Figure 8. UL RECOGNITION* The entire series including the bidirectional CA suffix has Underwriters Laboratory Recognition for the classification of protectors (QVGQ2) under the UL standard for safety 497B and File #E210057. Many competitors only have one or two devices recognized or have recognition in a non-protective category. Some competitors have no recognition at all. With the UL497B recognition, our parts successfully passed several tests including Strike Voltage Breakdown test, Endurance Conditioning, Temperature test, Dielectric Voltage-Withstand test, Discharge test and several more. Whereas, some competitors have only passed a flammability test for the package material, we have been recognized for much more to be included in their protector category. *Applies to P6KE6.8A − P6KE200A. |
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