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PIC18F85J10 Datasheet(PDF) 11 Page - Microchip Technology |
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PIC18F85J10 Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 410 page  © 2009 Microchip Technology Inc. DS39663F-page 9 PIC18F87J10 FAMILY FIGURE 1-2: PIC18F8XJ10/8XJ15 (80-PIN) BLOCK DIAGRAM PRODL PRODH 8 x 8 Multiply 8 BITOP 8 8 ALU<8> 8 8 3 W 8 8 8 Instruction Decode & Control Data Latch Address Latch Data Address<12> 12 Access BSR FSR0 FSR1 FSR2 inc/dec logic Address 4 12 4 PCH PCL PCLATH 8 31 Level Stack Program Counter Address Latch Program Memory (128 Kbytes) Data Latch 20 Table Pointer<21> inc/dec logic 21 8 Data Bus<8> Table Latch 8 IR 12 ROM Latch PCLATU PCU Instruction Bus <16> STKPTR Bank State Machine Control Signals Decode AD15:AD0, A19:A16 (Multiplexed with PORTD, PORTE and PORTH) PORTA PORTC PORTD PORTE PORTF PORTG RA0:RA5(1) RC0:RC7(1) RD0:RD7(1) RE0:RE7(1) RF1:RF7(1) RG0:RG4(1) PORTB RB0:RB7(1) PORTH RH0:RH7(1) PORTJ RJ0:RJ7(1) EUSART1 Comparators MSSP1 Timer2 Timer1 Timer3 Timer0 ECCP1 ADC 10-Bit EUSART2 ECCP2 ECCP3 MSSP2 CCP4 CCP5 Timer4 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. OSC1/CLKI OSC2/CLKO VDD, Timing Generation VSS MCLR Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) Precision Reference Band Gap INTRC Oscillator Regulator Voltage VDDCORE/VCAP ENVREG Data Memory (2.0, 3.9 Kbytes) |
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