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DNS10S0A0S20NFD Datasheet(PDF) 7 Page - Delta Electronics, Inc. |
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DNS10S0A0S20NFD Datasheet(HTML) 7 Page - Delta Electronics, Inc. |
7 / 16 page DS_DNL10SMD_07182012 7 TEST CONFIGURATIONS VI(+) VI(-) BATTERY ceramic L TO OSCILLOSCOPE 447uF × Note: Input reflected-ripple current is measured with a simulated source inductance. Current is measured at the input of the module. Figure 25: Input reflected-ripple test setup Vo GND COPPER STRIP 100uF ceramic 1uF ceramic SCOPE Resistive Load Note: Use a 100µF and 1µF ceramic capacitor. Scope measurement should be made using a BNC connector. Figure 26: Peak-peak output noise and startup transient measurement test setup SUPPLY I VI Vo GND Io LOAD CONTACT AND DISTRIBUTION LOSSES CONTACT RESISTANCE Figure 27: Output voltage and efficiency measurement test setup Note: All measurements are taken at the module terminals. When the module is not soldered (via socket), place Kelvin connections at module terminals to avoid measurement errors due to contact resistance. % 100 ) ( × × × = Ii Vi Io Vo η DESIGN CONSIDERATIONS Input Source Impedance To maintain low-noise and ripple at the input voltage, it is critical to use low ESR capacitors at the input to the module. The models using 4x47 uF very low ESR ceramic capacitors (MURATA P/N: GRM32ER61C476ME15L, 47uF/16V or equivalent) for example. The input capacitance should be able to handle an AC ripple current of at least: Arms Vin Vout Vin Vout Iout Irms − = 1 0 50 100 150 200 250 300 350 400 450 01 23 45 6 Output Voltage (Vdc) Ceramic Figure 28: Input ripple voltage vs. output models, Io = 20A (Cin = 4x22uF ceramic capacitors at the input) |
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