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CAT93C6612KI-28TE13 Datasheet(PDF) 7 Page - ON Semiconductor |
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CAT93C6612KI-28TE13 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 16 page CAT93C66, CAT93W66 http://onsemi.com 7 Write After receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66, CAT93W66 can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 6). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C66, CAT93W66 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Figure 4. EWEN/EWDS Instruction Timing CS DI STANDBY 10 0 * SK * ENABLE = 11 DISABLE = 00 Figure 5. Write Instruction Timing SK CS DI DO STANDBY HIGH−Z HIGH−Z 10 1 BUSY READY STATUS tHZ tEW tSV VERIFY AN−1 AN A0 D0 DN tCSMIN Figure 6. Erase Instruction Timing SK CS DI DO STANDBY HIGH−Z HIGH−Z 1 BUSY READY STATUS 11 VERIFY tHZ AN AN−1 A0 tCS tSV tEW |
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