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TPS62130RGTR Datasheet(PDF) 22 Page - Texas Instruments |
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TPS62130RGTR Datasheet(HTML) 22 Page - Texas Instruments |
22 / 36 page ÷ ÷ ø ö ç ç è æ + × × = 2 1 1 1 25 2 1 R R pF f pole p pF R f zero 25 2 1 1 × × = p TPS62130, TPS62130A TPS62131, TPS62132, TPS62133 SLVSAG7B – NOVEMBER 2011 – REVISED JUNE 2013 www.ti.com The TPS6213X devices, both fixed and adjustable versions, include an internal 25pF feedforward capacitor, connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors of the feedback divider, per equation Equation 13 and Equation 14: spacing (13) spacing (14) spacing Though the TPS6213X devices are stable without the pole and zero being in a particular location, adjusting their location to the specific needs of the application can provide better performance in Power Save mode and/or improved transient response. An external feedforward capacitor can also be added. A more detailed discussion on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466. Layout Considerations A proper layout is critical for the operation of a switched mode power supply, even more at high switching frequencies. Therefore the PCB layout of the TPS6213X demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation and noise sensitivity. See Figure 41 for the recommended layout of the TPS6213X, which is designed for common external ground connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output capacitor. Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated. Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g. SW). As they carry information about the output voltage, they should be connected as close as possible to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane. The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve appropriate power dissipation. The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the EVM Gerber data are available for download here, SLVC394. 22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: TPS62130, TPS62130A TPS62131 TPS62132 TPS62133 |
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