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XR16C850IJ Datasheet(PDF) 5 Page - Exar Corporation |
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XR16C850IJ Datasheet(HTML) 5 Page - Exar Corporation |
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5 / 56 page  xr XR16C850 REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 5 BAUD- OUT# 17 12 O Baud Rate Generator Output (active low). This pin provides the 16X clock of the selected data rate from the baud rate generator. The RCLK pin must be connected externally to BAUDOUT# when the receiver is operating at the same data rate. When the PC mode is selected, the baud rate generator clock output is internally connected to the RCLK input. This pin then functions as the printer port decode logic output (LPT1#), see Table 3. DDIS# 26 22 O Drive Disable Output. This pin goes to a logic 0 whenever the host CPU is reading data from the 850. It can control the direction of a data bus transceiver between the CPU and 850 or other logic functions. If 16 bit bus mode is selected, this pin becomes D12. During PC Mode, this pin becomes LPT2#. OP2# 35 31 O Output Port 2. General purpose output. During PC Mode, this pin becomes S3. PC MODE INTERFACE SIGNALS. CONNECT SEL PIN TO GND TO SELECT PC MODE. A3 25 20 I Address-3 Select Bit. This pin is used as the 4th address line to decode the COM1-4 and LPT ports. See Table 1 for details. During Intel Bus Mode, this pin becomes IOR. A4 12 6 I Address-4 Select Bit. This pin is used as the 5th address line to decode the COM1-4 and LPT ports. This pin has an internal 100k Ω pull-up resistor. This pin is not available on the 40-Pin PDIP package which operates in the Intel Bus Mode Only. See Table 1 for details. During Intel Bus Mode, this pin is inactive. A5 A6 A7 A8 14 15 16 21 9 10 11 17 I Address-5 thru Address-8 Select Bit. These pins are used as the 6th thru 9th address lines to decode the COM1-4 and LPT ports. See Table 1 for details. Dur- ing Intel Bus Mode, A5 becomes CS0, A6 becomes CS1, A7 becomes CS2#, and A8 becomes IOW. A9 1 37 I Address-9 Select Bit. This pin is used as the 10th address line to decode the COM1-4 and LPT ports. This pin has an internal 100k Ω pull-up resistor. This pin is not available on the 40-Pin PDIP package which operates in the Intel Bus Mode Only. See Table 1 for details. During Intel Bus Mode, this pin is inactive. AEN# 28 24 I Address Enable input (active low). When AEN# transitions to logic 0, it decodes and validates COM 1-4 ports address per S1, S2 and S3 inputs. During Intel Bus Mode, this pin becomes AS#. S1 S2 S3 23 10 35 21 5 31 I Select 1 to 3. These are the standard PC COM 1-4 ports and IRQ selection inputs. See Table 1 and Table 3 for details. The S1 pin has an internal 100kΩ pull-up resistor. This pin is not available on the 40 pin PDIP packages which operates in the Intel Bus Mode Only. During Intel Bus Mode, S1 is inactive, S2 becomes RCLK, and S3 becomes OP2#. IRQA IRQB IRQC 33 32 27 30 29 23 O Interrupt Request A, B and C Outputs (active high, three-state). These are the interrupt outputs associated with COM 1-4 to be connected to the host data bus. See interrupt section for details. The Interrupt Requests A, B or C functions as IRQx to the PC bus. IRQx is enabled by setting MCR bit-3 to logic 1 and the desired interrupt(s) in the interrupt enable register (IER). During Intel Bus Mode, IRQA becomes INT, IRQB becomes RXRDY#, and IRQC becomes TXRDY#. LPT1# 17 12 O Line Printer Port-1 Decode Logic Output (active low). This pin functions as the PC standard LPT-1 printer port address decode logic output, see Table 1. The baud rate generator clock output, BAUDOUT#, is internally connected to the RCLK input in the PC mode. During Intel Bus Mode, LPT1# becomes BAUDOUT#. NAME 44-PIN PLCC 48-PIN TQFP TYPE DESCRIPTION |
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