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XR16C850CJ Datasheet(PDF) 3 Page - Exar Corporation |
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XR16C850CJ Datasheet(HTML) 3 Page - Exar Corporation |
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3 / 56 page  xr XR16C850 REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 3 PIN DESCRIPTIONS NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE DEVICE STATUS XR16C850CJ 44-Lead PLCC 0°C to +70°C Active XR16C850CM 48-Lead TQFP 0°C to +70°C Active XR16C850IJ 44-Lead PLCC -40°C to +85°C Active XR16C850IM 48-Lead TQFP -40°C to +85°C Active NAME 44-PIN PLCC 48-PIN TQFP TYPE DESCRIPTION INTEL BUS MODE INTERFACE. THE SEL PIN IS CONNECTED TO VCC. A2 A1 A0 29 30 31 26 27 28 I Address data lines [2:0]. A2:A0 selects internal UART’s configuration registers. D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 43 44 45 46 47 2 3 4 I/O Data bus lines [7:0] (bidirectional). IOR# 24 19 I Input/Output Read (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A2:A0], places it on the data bus to allow the host processor to read it on the lead- ing edge. Either an active IOR# or IOR is required to transfer data from 850 to CPU during a read operation. If not used, connect this pin to VCC. Caution: SEE”FAC- TORY TEST MODE” ON PAGE 7. IOR 25 20 I Input/Output Read (active high). Same as IOR# but active high. Either an active IOR# or IOR is required to transfer data from 850 to CPU during a read operation. If not used, connect this pin to GND. During PC Mode, this pin becomes A3. Cau- tion: SEE”FACTORY TEST MODE” ON PAGE 7. IOW# 20 16 I Input/Output Write (active low). The falling edge instigates the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to transfer data from 850 to the Intel type CPU during a write operation. If not used, connect this pin to VCC. Caution: SEE”FACTORY TEST MODE” ON PAGE 7. IOW 21 17 I Input/Output Write (active high). The rising edge instigates the internal write cycle and the falling edge transfers the data byte on the data bus to an internal register pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to transfer data from 850 to the Intel type CPU during a write operation. During PC Mode, this pin becomes A8. If not used, connect this pin to GND. Caution: SEE”FACTORY TEST MODE” ON PAGE 7. |
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